Fig. 1.
The conventional current-mode RF front-end schematic
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| Citation: |
Songting Li, Jiancheng Li, Xiaochen Gu, Hongyi Wang, Zhaowen Zhuang. A high linearity downconverter for digital broadcasting system[J]. Journal of Semiconductors, 2014, 35(12): 125010. doi: 10.1088/1674-4926/35/12/125010
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S T Li, J C Li, X C Gu, H Y Wang, Z W Zhuang. A high linearity downconverter for digital broadcasting system[J]. J. Semicond., 2014, 35(12): 125010. doi: 10.1088/1674-4926/35/12/125010.
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A high linearity downconverter for digital broadcasting system
DOI: 10.1088/1674-4926/35/12/125010
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Abstract
An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 μm CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an ⅡP2 of 63 dBm, an ⅡP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 mA under a supply of 1.2 V. -
References
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