J. Semicond. > 2014, Volume 35 > Issue 2 > 024004
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SEMICONDUCTOR DEVICES

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

Lijuan Wu1, 2, , Wentong Zhang2, Bo Zhang2 and Zhaoji Li2

+ Author Affiliations

 Corresponding author: Wu Lijuan, ljwu@cuit.edu.cn

DOI: 10.1088/1674-4926/35/2/024004

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Abstract: A new SOI self-balance (SB) super-junction (SJ) pLDMOS with a self-adaptive charge (SAC) layer and its physical model are presented. The SB is an effective way to realize charges balance (CB). The substrate-assisted depletion (SAD) effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field (EI) of the dielectric buried layer and increase breakdown voltage (BV). EI=600 V/μm and BV=-237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance (Ron, sp) of 0.01319 Ω·cm2, FOM (FOM=BV2/Ron, sp) of 4.26 MW/cm2 under a 11 μm length (Ld) drift region.

Key words: self-adaptive charge, self-balance, charge balance, super-junction, substrate-assisted depletion



[1]
Nassif-Khalil S G, Salama C A T. Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST). Proc ISPSD, 2002:81 http://ieeexplore.ieee.org/abstract/document/1016176/
[2]
Ng R, Udrea F, Sheng K, et al. Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI. Proc IEEE ISPSD, 2001:395 http://ieeexplore.ieee.org/document/934637/keywords
[3]
Chen Y, Buddharaju K D, Liang Y C, et al. Super junction power LDMOS on partial SOI platform. Proc ISPSD, California, USA, 2007:177 http://ieeexplore.ieee.org/document/5250425/
[4]
Chen W, Zhang B, Li Z. Optimization of super-junction SOI-LDMOS with a step doping surface-implanted layer. Semicond Sci Technol, 2007, 22(3):464 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.baztech-article-LOD6-0019-0001
[5]
Wang W, Zhang B, Li Z, et al. High-voltage SOI SJ-LDMOS with a nondepletion compensation layer. IEEE Electron Device Lett, 2009, 30(1):68 doi: 10.1109/LED.2008.2008208
[6]
Zhang B, Li Z, Hu S, et al. Field enhancement for dielectric layer of high-voltage devices on silicon on insulator. IEEE Trans Electron Devices, 2009, 56(10):2327 doi: 10.1109/TED.2009.2028405
[7]
Li Z, Luo X, Zhang B, et al. The enhancement of dielectric layer field of SOI high voltage devices. Fourth Joint Symposium on Opto-and Microelectronic Devices and Circuits, 2006:61 http://ieeexplore.ieee.org/abstract/document/4348285/
[8]
Luo Xiaorong, Zhang Bo, Li Zhaoji, et al. A novel SOI high voltage device structure with partial locating charge trench. Chinese Journal of Semiconductors, 2006, 27(1):115 http://en.cnki.com.cn/Article_en/CJFDTOTAL-BDTX200307015.htm
[9]
ISE TCAD Manuals. release 10. 0
[10]
Sze S M, Ng K K. Physics of semiconductor devices. 3rd ed. New York: A John Wiley and Sons, 2007
Fig. 1.  Structure and mechanism of SB SOI SJ-pLDMOS. (a) Three-dimensional view of the SB SOI SJ-pLDMOS, with alternating P and N drift regions and $L_{\rm d}$ $=$ 11 $\mu$m, $t_{\rm I}$ $=$ 0.375 $\mu$m, and $D=W$ $=$ 0.5 $\mu$m, $H$ $=$ 1 $\mu $m, $W_{\rm p}$ $=$ $W_{\rm n}$ $=$ 1 $\mu$m, and $N_{\rm n}$ $=$ $N_{\rm p}$ $=$ 4 $\times$ 10$^{16}$ cm$^{-3}$, $t_{\rm s}$ $=$ 1 $\mu$m, $t_{\rm b}$ $=$ 1.5 $\mu$m, $N_{\rm sub}$ $=$ 2.4 $\times$ 10$^{14}$ cm$^{-3}$. (b) Cross section along the AA' plane of the SB SOI SJ-pLDMOS. Plentiful electrons are located on the top interface whose concentration increases from the source to the drain with potential.

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Fig. 2.  The electron concentration distributions of SB and P$^{+}$I. (a) 2D-view of electron concentration on the interfaces for SB (BV $=$ $-237$ V)(b) 2D-view of electron concentration on the interfaces for P$^{+}$I (BV $=$ $-150$ V).

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Fig. 3.  The interface charges of an SOI SJ LDMOS based on the ENDIF

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Fig. 4.  The equipotential contour distributions of the two structures. (a) The equipotential contour distribution of the SB SOI, BV $=$ $-237$ V. (b) The equipotential contour distribution of the p-buffer conventional SOI, BV $=$ $-82$ V.

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Fig. 5.  The surface ($y=$ 0.01 $\mu$m) and interface ($y=$ 2.6 $\mu$m) electric field profiles at breakdown voltage (BV $=$ $-237$ V, $-82$ V and $-48$V for three structures, respectively). (a) The surface ($y=$ 0.001 $\mu$m) electric field profiles at breakdown voltage with $L_{\rm d}$ $=$ 11 $\mu$m for the SB SOI SJ-pLDMOS, the p-buffer SOI SJ-LDMOS and the Con SOI SJ-LDMOS. (b) The dielectric ($y=$ 2.6 $\mu$m) electric field profiles at breakdown for the SB SOI SJ-pLDMOS, the p-buffer SOI SJ-LDMOS and the Con SOI SJ-LDMOS.

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Fig. 6.  Vertical electric field and potential profiles of three structures, respectively ($E_{\rm I}$ $=$ 600 V/$\mu$m, 98 V/$\mu$m for the SB SOI SJ-pLDMOS and the Con SOI SJ-LDMOS). (a) The vertical electric fields of the proposed, p-buffer, and conventional devices with the buried oxide thickness of 0.375 $\mu$m. (b) The potential profiles the drain end for the proposed, p-buffer, and conventional devices with the buried oxide thickness of 0.375$\mu$m.

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Fig. 7.  The effect of the structural parameters on the voltage. (a) BV versus $L_{\rm d}$ and $N_{\rm d}$ in SB SJ-LDMOS and Con SOI SJ. (b) BV versus $D$, $W$ and $H$.

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[1]
Nassif-Khalil S G, Salama C A T. Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST). Proc ISPSD, 2002:81 http://ieeexplore.ieee.org/abstract/document/1016176/
[2]
Ng R, Udrea F, Sheng K, et al. Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI. Proc IEEE ISPSD, 2001:395 http://ieeexplore.ieee.org/document/934637/keywords
[3]
Chen Y, Buddharaju K D, Liang Y C, et al. Super junction power LDMOS on partial SOI platform. Proc ISPSD, California, USA, 2007:177 http://ieeexplore.ieee.org/document/5250425/
[4]
Chen W, Zhang B, Li Z. Optimization of super-junction SOI-LDMOS with a step doping surface-implanted layer. Semicond Sci Technol, 2007, 22(3):464 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.baztech-article-LOD6-0019-0001
[5]
Wang W, Zhang B, Li Z, et al. High-voltage SOI SJ-LDMOS with a nondepletion compensation layer. IEEE Electron Device Lett, 2009, 30(1):68 doi: 10.1109/LED.2008.2008208
[6]
Zhang B, Li Z, Hu S, et al. Field enhancement for dielectric layer of high-voltage devices on silicon on insulator. IEEE Trans Electron Devices, 2009, 56(10):2327 doi: 10.1109/TED.2009.2028405
[7]
Li Z, Luo X, Zhang B, et al. The enhancement of dielectric layer field of SOI high voltage devices. Fourth Joint Symposium on Opto-and Microelectronic Devices and Circuits, 2006:61 http://ieeexplore.ieee.org/abstract/document/4348285/
[8]
Luo Xiaorong, Zhang Bo, Li Zhaoji, et al. A novel SOI high voltage device structure with partial locating charge trench. Chinese Journal of Semiconductors, 2006, 27(1):115 http://en.cnki.com.cn/Article_en/CJFDTOTAL-BDTX200307015.htm
[9]
ISE TCAD Manuals. release 10. 0
[10]
Sze S M, Ng K K. Physics of semiconductor devices. 3rd ed. New York: A John Wiley and Sons, 2007

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    Received: 08 July 2013 Revised: 10 August 2013 Online: Published: 01 February 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(2): 024004
      Lijuan Wu, Wentong Zhang, Bo Zhang, Zhaoji Li. A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance[J]. Journal of Semiconductors, 2014, 35(2): 024004. doi: 10.1088/1674-4926/35/2/024004 ****L J Wu, W T Zhang, B Zhang, Z J Li. A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance[J]. J. Semicond., 2014, 35(2): 024004. doi: 10.1088/1674-4926/35/2/024004.
      Citation:
      Lijuan Wu, Wentong Zhang, Bo Zhang, Zhaoji Li. A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance[J]. Journal of Semiconductors, 2014, 35(2): 024004. doi: 10.1088/1674-4926/35/2/024004 ****
      L J Wu, W T Zhang, B Zhang, Z J Li. A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance[J]. J. Semicond., 2014, 35(2): 024004. doi: 10.1088/1674-4926/35/2/024004.
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      A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

      DOI: 10.1088/1674-4926/35/2/024004
      • 1.

        College of Communication Engineering, Chengdu University of Information Technology, Chengdu 610225, China

      • 2.

        State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      Funds:

      the National Natural Science Foundation of China 61306094

      the Research Fund for the Middle and Youth Academic Leader of Chengdu University of Information Technology J201301

      the Project of Sichuan Provincial Education Department 13ZA0089

      Project supported by the National Natural Science Foundation of China (No. 61306094), the Project of Sichuan Provincial Education Department (No. 13ZA0089), and the Research Fund for the Middle and Youth Academic Leader of Chengdu University of Information Technology (No. J201301)

      More Information
      • Corresponding author: Wu Lijuan, ljwu@cuit.edu.cn
      • Received Date: 2013-07-08
      • Revised Date: 2013-08-10
      • Published Date: 2014-02-01

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