J. Semicond. > 2014, Volume 35 > Issue 3 > 034003
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SEMICONDUCTOR DEVICES

A laterally graded junctionless transistor

Punyasloka Bal1, Bahniman Ghosh1, 2, Partha Mondal1 and M. W. Akram1,

+ Author Affiliations

 Corresponding author: M. W. Akram, Email:mwakram@iitk.ac.in

DOI: 10.1088/1674-4926/35/3/034003

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Abstract: This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the IOFF and ION/IOFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state, which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.

Key words: junctionless field effect transistor, laterally graded, subthreshold slope



[1]
Lilienfeld J E. Method and apparatus for controlling electric current. USA Patent, No. 1745175, Oct. 22, 1925
[2]
Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors without junctions. Nat Nanotechnol, 2010, 5(3):225 doi: 10.1038/nnano.2010.15
[3]
Lee C W, Afzalian A, Akhavan N D, et al. Junctionless multigate field-effect transistor. Appl Phys Lett, 2009, 94(5):053511 doi: 10.1063/1.3079411
[4]
Lee C W, Ferain I, Kranti A, et al. Short-channel junctionless nanowire transistors. Proc SSDM, 2010:1044 https://confit.atlas.jp/guide/organizer/ssdm/ssdm2010/subject/C-9-5L/search;jsessionid=80FE6AFBC1182DB5EF96DB6241AD7880?eventCode=ssdm2010&code=C-9-5L
[5]
Kranti A, Yan R, Lee C W, et al. Junctionless nanowire transistor (JNT):properties and design guidelines. Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2010:357 http://www.sciencedirect.com/science/article/pii/S0038110111002139?via%3Dihub
[6]
Su C J, Tsai T I, Liou Y L, et al. Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett, 2011, 32(4):521 doi: 10.1109/LED.2011.2107498
[7]
Gundapaneni S, Bajaj M, Pandey R K, et al. Effect of band-to-band tunneling on junctionless transistors. IEEE Electron Device Lett, 2012, 59(4):1023 doi: 10.1109/TED.2012.2185800
[8]
Choi S J, Moon D I, Kim S, et al. Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett, 2011, 32(5):602 doi: 10.1109/LED.2011.2118734
[9]
Lee C W, Yan R, Ferain I, et al. Nanowire zero-capacitor DRAM transistors with and without junctions. Proc 10th IEEE-NANO, 2010:242 http://ieeexplore.ieee.org/abstract/document/5697888/
[10]
Kranti A, Lee C, Ferain I, et al. Junctionless 6T SRAM cell. IET Electron Lett, 2010, 46(22):1491 doi: 10.1049/el.2010.2736
[11]
Sels D, Sore B, Groeseneken G. Quantum ballistic transport in the junctionless nanowire pinch-off field effect transistor. J Comput Electron, 2011, 10(1/2):216 http://www.refdoc.fr/Detailnotice?cpsidt=24145533
[12]
Silvaco, Version 5. 15. 32. R. (2009)[Online]. Available: http://www.silvaco.com
Fig. 1.  Schematic structure of double gate JLFET.

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Fig. 2.  2-D graded doping profile of double gate JLFET with peak doping near source and drain region, $L_{\rm g}$ $=$ 25 nm, $N_{\rm p}$ $=$ 1 $\times$ 10$^{19}$ cm$^{-3}$.

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Fig. 3.  $I_{\rm D}$ versus $V_{\rm G}$ plot of the GDP DGJLFET for different characteristic lengths of the Gaussian doping profile. $V_{\rm DD}$ $=$ 1 V, $L_{\rm g}$ $=$ 25 nm, $N_{\rm d}$ $=$ 1 $\times$ 10$^{19}$ cm$^{-3}$.

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Fig. 4.  Gate to source capacitance versus gate voltage plot of the GDP DGJLFET for different characteristic lengths of the Gaussian doping profile. AC freq $=$ 1 MHz.

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Fig. 5.  $I_{\rm DS}$-$V_{\rm GS}$ characteristics of a 25-nm channel length uniformly doped DGJLFET (UDP) and Gaussian doped DGJLFET (GDP). $V_{\rm DD}$ $=$ 0.05 V and 1 V, characteristic length $=$ 8 nm.

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Fig. 6.  ON current and OFF current of the GDP DGJLFET and UDP DGJLFET for different gate lengths. $V_{\rm DD}$ $=$ 1 V, characteristic length $=$ 8 nm.

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Fig. 7.  ON state current and OFF state current for different characteristic lengths of Gaussian doping (1.414$\sigma )$ for 25 nm gate length and $V_{\rm DD}$ $=$ 1 V. Inset: ON to OFF state current ratio for different characteristic lengths, while keeping all other parameters the same for both the devices.

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Table 1.   Parameters for device simulation.
[1]
Lilienfeld J E. Method and apparatus for controlling electric current. USA Patent, No. 1745175, Oct. 22, 1925
[2]
Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors without junctions. Nat Nanotechnol, 2010, 5(3):225 doi: 10.1038/nnano.2010.15
[3]
Lee C W, Afzalian A, Akhavan N D, et al. Junctionless multigate field-effect transistor. Appl Phys Lett, 2009, 94(5):053511 doi: 10.1063/1.3079411
[4]
Lee C W, Ferain I, Kranti A, et al. Short-channel junctionless nanowire transistors. Proc SSDM, 2010:1044 https://confit.atlas.jp/guide/organizer/ssdm/ssdm2010/subject/C-9-5L/search;jsessionid=80FE6AFBC1182DB5EF96DB6241AD7880?eventCode=ssdm2010&code=C-9-5L
[5]
Kranti A, Yan R, Lee C W, et al. Junctionless nanowire transistor (JNT):properties and design guidelines. Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2010:357 http://www.sciencedirect.com/science/article/pii/S0038110111002139?via%3Dihub
[6]
Su C J, Tsai T I, Liou Y L, et al. Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett, 2011, 32(4):521 doi: 10.1109/LED.2011.2107498
[7]
Gundapaneni S, Bajaj M, Pandey R K, et al. Effect of band-to-band tunneling on junctionless transistors. IEEE Electron Device Lett, 2012, 59(4):1023 doi: 10.1109/TED.2012.2185800
[8]
Choi S J, Moon D I, Kim S, et al. Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett, 2011, 32(5):602 doi: 10.1109/LED.2011.2118734
[9]
Lee C W, Yan R, Ferain I, et al. Nanowire zero-capacitor DRAM transistors with and without junctions. Proc 10th IEEE-NANO, 2010:242 http://ieeexplore.ieee.org/abstract/document/5697888/
[10]
Kranti A, Lee C, Ferain I, et al. Junctionless 6T SRAM cell. IET Electron Lett, 2010, 46(22):1491 doi: 10.1049/el.2010.2736
[11]
Sels D, Sore B, Groeseneken G. Quantum ballistic transport in the junctionless nanowire pinch-off field effect transistor. J Comput Electron, 2011, 10(1/2):216 http://www.refdoc.fr/Detailnotice?cpsidt=24145533
[12]
Silvaco, Version 5. 15. 32. R. (2009)[Online]. Available: http://www.silvaco.com

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    Received: 19 July 2013 Revised: Online: Published: 01 March 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(3): 034003
      Punyasloka Bal, Bahniman Ghosh, Partha Mondal, M. W. Akram. A laterally graded junctionless transistor[J]. Journal of Semiconductors, 2014, 35(3): 034003. doi: 10.1088/1674-4926/35/3/034003 ****P Bal, B Ghosh, P Mondal, M. W. Akram. A laterally graded junctionless transistor[J]. J. Semicond., 2014, 35(3): 034003. doi: 10.1088/1674-4926/35/3/034003.
      Citation:
      Punyasloka Bal, Bahniman Ghosh, Partha Mondal, M. W. Akram. A laterally graded junctionless transistor[J]. Journal of Semiconductors, 2014, 35(3): 034003. doi: 10.1088/1674-4926/35/3/034003 ****
      P Bal, B Ghosh, P Mondal, M. W. Akram. A laterally graded junctionless transistor[J]. J. Semicond., 2014, 35(3): 034003. doi: 10.1088/1674-4926/35/3/034003.
      shu

      A laterally graded junctionless transistor

      DOI: 10.1088/1674-4926/35/3/034003
      • 1.

        Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

      • 2.

        Microelectronics Research Center, 10100 Burnet Road, University of Texas at Austin, Austin, TX, 78758, USA

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      • Corresponding author: M. W. Akram, Email:mwakram@iitk.ac.in
      • Received Date: 2013-07-19
      • Published Date: 2014-03-01

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