1. Introduction

The boost DC-DC converter, which is able to deliver a high output voltage with a very low power supply^[1-3], is widely used for mobile applications owing to its favorable characteristics, such as high efficiency, low quiescent current, small size, wide range of input voltage and excellent driving capacity^[4-7]. However, the DC-DC converter operates in switch mode, especially when the converter works in discontinuous conduction mode (DCM), ringing occurs. On one hand, ringing lowers the power efficiency; on the other hand, ringing causes large switching noise and serious electromagnetic interference (EMI). EMI noise may be radiated in free space and damage the radio frequency (RF) circuits. Now, some passive and active EMI filtering methods^{[8, 9]} are presented to attenuate the EMI noise, but those techniques increase the size and the cost of a printed circuit board (PCB), which is not suitable for portable applications. In Ref. [10], a time varying resistor network, which is connected between the switching node and the power supply of the DC-DC converter, is proposed to solve this problem. Unfortunately, the time varying resistor network should be carefully designed to achieve its best function, which requires a complicated control circuit and the die size will be increased. Meanwhile, the light load efficiency is decreased when this method is used.

In this paper, a novel boost DC-DC converter with an adaptive dead time control circuit and anti-ringing circuit is presented. By this technique, the EMI noise is effectively suppressed and high power efficiency is achieved. Section 2 describes the formation of ringing when boost DC-DC converter operates in DCM. Section 3 analyzes the working principle of the proposed boost converter thoroughly. The experimental results are presented in Section 4 and the conclusions are given in Section 5.

2. Ringing formation

Figure 1 shows the schematic of a conventional synchronous boost DC-DC converter: $V_{\rm IN}$ represents the power supply and $V_{\rm O}$ is the output; $L$ is an energy transferring inductor; $C_{\rm O}$ is an output filtering capacitor; $R_{\rm L}$ is the load resistor; $C_{\rm X}$ is the parasitic capacitor at node $V_{\rm LX}$; and $I_{\rm L}$ stands for the current through the inductor $L$. Normally, to achieve low on-resistance and high efficiency, the power switches MN and MP are always very large, so $C_{\rm X}$ cannot be ignored. There are three main stages when the boost converter works in DCM. Figure 2 illustrates the timing diagram and equivalent circuits.

During stage 1 ($t_{0}$ < $t$ < $t_{1})$, MN is on and MP is off. $V_{\rm LX}$ and $C_{\rm X}$ are shorted to ground. $I_{\rm L}$ ramps up at a slope of $V_{\rm IN}/L$ from zero and the energy stored in inductor L also increases.

During stage 2 ($t_{1}$ < $t$ < $t_{2})$, MN is off and MP is on. $V_{\rm LX}$ is equal to $V_{\rm O}$ and $C_{\rm X}$ is paralleled with output capacitor $C_{\rm O}$. $I_{\rm L}$ ramps down at a slope of ($V_{\rm IN}$ -$V_{\rm O})/L$ and flows into the output $V_{\rm O}$. The energy stored in inductor L depletes gradually. At the end of this stage, $I_{\rm L}$ decreases to zero.

During stage 3 ($t_{2}$ < $t$ < $t_{3})$, both MN and MP are off. Inductor L and parasitic capacitor $C_{\rm X}$ form a resonant tank. Ringing will appear at the $V_{\rm LX}$ node, causing large EMI in the system. In this stage, the following equations can be obtained:

$\begin{equation} I_{\rm L} (t)=C_{\rm X} \frac{{\rm d}V_{\rm LX} (t)}{{\rm d}t}, \end{equation}$

(1)

$\begin{equation} V_{\rm IN} -V_{\rm LX} (t)=L\frac{{\rm d}I_{\rm L} (t)}{{\rm d}t}. \end{equation}$

(2)

According to Eqs. (1) and (2), we can get

$\begin{equation} \frac{{\rm d}^2V_{\rm LX} (t)}{{\rm d}t^2}+\frac{1}{LC_{\rm X} }V_{\rm LX} (t)=\frac{1}{LC_{\rm X} }V_{\rm IN} . \end{equation}$

(3)

Moreover

$\begin{equation} V_{\rm LX} (t_2 )=V_{\rm O}, \end{equation}$

(4)

$\begin{equation} {V}'_{\rm LX} (t_2 )=\frac{1}{C_{\rm X} }I_{\rm L} (t_2 )=0. \end{equation}$

(5)

From Eqs. (3)-(5), the resonant voltage at node $V_{\rm LX}$ can be given by

$\begin{equation} V_{\rm LX} \left( t \right)=V_{\rm IN} +\left( {V_{\rm O} -V_{\rm IN} } \right) \cos \omega _0 \left( {t-t_2 } \right), \quad t_2 \leqslant t\leqslant t_3, \end{equation}$

(6)

and the resonant current can be derived as

$\begin{equation} I_{\rm L} \left( t \right)=\frac{V_{\rm IN} -V_{\rm O}}{\omega _0 L}\sin \omega _0 \left( {t-t_2 } \right), \quad t_2 \leqslant t\leqslant t_3, \end{equation}$

(7)

where $\omega_{0}$ is calculated by

$\begin{equation} \omega _0 =\frac{1}{\sqrt {LC_{\rm X} } }. \end{equation}$

(8)

Today and in the future, small-value off-chip inductors^{[11, 12]} or even on-chip inductors^[13] are and will be widely used for portable applications to achieve small size and low cost. Thus, the oscillation frequency at the $V_{\rm LX}$ node gets higher and higher. Large ringing and EMI noise may seriously affect RF circuits and decrease the power efficiency. In addition, the resonant current sinks and sources current from $V_{\rm IN}$ repeatedly, which therefore results in poor stability of the power supply.

3. Proposed Boost DC-DC converter

3.1 Architecture

In order to suppress the ringing and improve the power efficiency, as shown in Fig. 3(a), a novel boost converter with a dead time control (DTC) circuit and an anti-ringing circuit is proposed. D is the body diode of the P-channel metal-oxide semiconductor (PMOS) switch MP. The substrate of the MP should be connected to the highest voltage of the boost converter $V_{\rm O}$ and the substrate of the N-channel metal-oxide semiconductor (NMOS) switch MN should be tied to the ground to make sure the normal operation of DC-DC converter. A compensation block^[14-18] ensures the stability of the converter and the pulse width modulator (PWM) module provides the duty cycle. The soft-start signal $V_{\rm START}$ minimizes the inrush current and the output overshoot during normal startup. Timing diagram of the proposed converter is shown in Fig. 3(b), which is different from the timing diagram of a conventional converter shown in Fig. 2(a) in two aspects.

(1) Dead time, during which the power transistors MP and MN are both off, is added to reduce shoot-through current loss, body diode conduction loss and charge-sharing loss; the DTC circuit provides an optimal dead time. Moreover, the DTC circuit can avoid the reverse inductor current from lowering the power efficiency when the inductor current reaches zero.

(2) During stage 3, ringing is eliminated by the anti-ringing circuit based on the switching sequence of power transistors. Therefore, low EMI and high efficiency can be achieved.

3.2 DTC circuit

The power switches MN and MP always have very low on-resistances for the purpose of obtaining high efficiency, so MN and MP should not conduct at the same time to avoid a large shoot-through current that greatly degrades the efficiency and causes large glitches in the inductor current and output voltage. To solve this problem, a dead time between stages 1 and 2 is needed. During the dead time, both MN and MP are off. Inductor current $I_{\rm L}$ charges the parasitic capacitor $C_{\rm X}$ and $V_{\rm LX}$ goes up from zero. It should be noted that the optimal dead time $T_{\rm OPT}$ is related to the load condition and should satisfy the equation as follows:

$\begin{equation} T_{\rm OPT} =\frac{V_{\rm O} C_{\rm X} }{I_{\rm PEAK} }, \end{equation}$

(9)

where $I_{\rm PEAK}$ is the peak inductor current, which is proportional to the load current and thus $T_{\rm OPT}$ is finally determined by the load current when $V_{\rm O}$ and $C_{\rm X}$ are given. If the dead time is fixed as $\Delta T$ and $\Delta T$ is designed according to the medium load of the converter, extra power losses caused by the charge-sharing and the body diode conduction will be introduced, which can easily be understood as follows.

(1) Body diode conduction loss. As shown in Fig. 4(a), assuming the load current is very large and hence the fixed dead time $\Delta T$ is much longer than the optimal dead time $T_{\rm OPT}$, the body diode D will conduct and $V_{\rm LX}$ will be clamped to $V_{\rm O} + V_{\rm D}$ (forward voltage drop of diode D). Since the voltage drop across the body diode is much higher than that across the power switch MP, conversion efficiency is decreased due to the body diode conduction loss.

(2) Charge-sharing loss. As shown in Fig. 4(b), if the load current is very small and hence $\Delta T$ is much shorter than $T_{\rm OPT}$, MP will be turned on before $V_{\rm LX}$ reaches $V_{\rm O}$. Energy stored in the output capacitor $C_{\rm O}$ will charge $C_{\rm X}$ until $V_{\rm LX}$ goes up to $V_{\rm O}$. That is to say, the energy stored in $C_{\rm O}$ for the load is depleted because of the charge-sharing loss. As a result, a dynamic dead time optimization is required.

In this design, a DTC circuit that can provide an adaptive dead time is presented. Compared with dead time optimization methods^{[19, 20]} that need complex algorithms to find out the optimal dead time, the proposed DTC circuit can easily adjust the dead time depending on the load current with a very compact structure. As shown in Fig. 5, the DTC circuit is composed of transistors M1-M9, a driver and a constant current source $I_{\rm B}$. The sources of M2 and M5 are connected to the node $V_{\rm LX}$ while the sources of M1, M3 and M4 are connected to $V_{\rm O}$. The aspect ratios of M1-M9 are designed as follows:

$\begin{equation} \left( {\frac{W}{L}} \right)_{\rm M2, 3} =K_1 \left( {\frac{W}{L}} \right)_{\rm M1}, \end{equation}$

(10)

$\begin{equation} \left( {\frac{W}{L}} \right)_{\rm M4} =\left( {\frac{W}{L}} \right)_{\rm M5}, \end{equation}$

(11)

$\begin{equation} \left( {\frac{W}{L}} \right)_{\rm M6, 9} =K_2 \left( {\frac{W}{L}} \right)_{\rm M7, 8}, \end{equation}$

(12)

where $K_{1} >$ 1 and $K_{2} >$ 1.

Figure 6 shows the simulation results of the proposed DTC circuit. As mentioned before, at the end of stage 1, MN is turned off immediately and $V_{\rm LX}$ goes up from zero. Once $V_{\rm LX}$ > $V_{\rm O}$, current $I_{2}$ goes larger than current $I_{3}$ because source-to-gate voltage of M2 is higher than that of M3. Since $I_{6} = K_{2}I_{2}$ and $I_{5} = K_{2}I_{3}$, $I_{6}$ > $I_{5}$. Moreover, $I_{5}$ > $I_{4}$, $I_{6}$ is thus much larger than $I_{4}$ and the voltage at node $V_{\rm A}$ drops to zero rapidly, as shown in Fig. 6(a). MP will be turned on and then stage 2 starts. Therefore, adaptive dead time control is achieved. On the contrary, at the end of stage 2, if a reverse inductor current happens, $V_{\rm LX}$ < $V_{\rm O}$ and the $V_{\rm A}$ node voltage pulls up to high quickly, as shown in Fig. 6(b). MP is turned off and then stage 3 begins, which prevents the reverse inductor current loss from lowering the power efficiency.

3.3 Anti-ringing circuit

From Fig. 2(a), ringing occurs during stage 3, causing large EMI. To overcome this drawback, a novel anti-ringing circuit is developed. As shown in Fig. 7, the circuit consists of two level shifters, a PMOS switch MS, a buffer and a dead time detection (DTD) circuit. The substrate of MS is biased by $V_{\rm O}$. When both MN and MP are off in stage 3, M$_{\rm S}$ is turned on. The oscillation loop is broken by shorting the inductor L and hence ringing is effectively suppressed.

The difficulty of designing the anti-ringing circuit is to generate a proper drive signal to make sure MS is turned on only in stage 3 without affecting the operation of the converter in other stages. It is obvious that both MN and MP are also off during the dead time. If control signal $V_{\rm C1}$ is decided only by the states of MN and MP, MS will conduct in dead time and the energy stored in inductor $L$ will be wasted by the on-resistance of MS instead of transferring to $V_{\rm O}$, which results in large power loss. To overcome this problem, a DTD circuit is used. From Fig. 7, output signal $V_{\rm C}$ of the DTD circuit is related to the state of $Q$ besides the states of MN and MP. $V_{\rm C}$ is first converted by the level shifter and then buffered to get $V_{\rm C1}$ to control MS. Table 1 shows the state transition table of the proposed DTD circuit. It can be seen from the table that though both MN and MP have the same states in stage 3 and dead time, the state of $Q$ is different and therefore MS is switched on only in stage 3. Furthermore, the proposed DTD circuit is very compact and nearly has no time delay. Figure 8 shows the simulation results of the proposed anti-ringing circuit. From the results, during the operation period $T$, drive signal $V_{\rm C}$ is low only in stage 3, which agrees with the theory analysis above.

It should be noted that drive signals $V_{\rm C1}$ and $V_{\rm P}$ should be powered by $V_{\rm O}$, which is the highest voltage of the converter. However, $V_{\rm N}$ and the DTD circuit are powered by $V_{\rm IN}$, so a level shifter is needed to achieve the conversion of different voltage levels. The schematic and timing diagram are shown in Fig. 9.

A boost converter with the proposed anti-ringing circuit is simulated and the simulation is conducted with the following typical application condition: $V_{\rm IN}$ $=$ 3.3 V, $V_{\rm O}$ $=$ 4.6 V, $L =$ 1.5 $\mu$H, $C_{\rm O}$ $=$ 4.7 $\mu$F, clock frequency $f_{\rm S}$ $=$ 1.6 MHz and temperature $T_{\rm A}$ $=$ 25 ℃. A high switching frequency ensures a small-value off-chip inductor can be used. In order to verify the advantages of the proposed boost converter, simulation of a boost converter without an anti-ringing circuit is also performed and the results are shown in Fig. 10(a). From the results, ringing occurs when the converter operates in DCM. Figure 10(b) shows the results of the proposed boost DC-DC converter and that the ringing is effectively suppressed with the developed anti-ringing circuit.

4. Experimental results

The designed boost DC-DC converter with both the proposed DTC circuit and the proposed anti-ringing circuit has been fabricated using the 0.6 $\mu$m CDMOS process. Figure 11 shows the micrograph of the proposed converter and the die size is about 2.2 $\times$ 1.5 mm$^{2}$. The total area of the DTC circuit and anti-ringing circuit is only 0.03 mm$^{2}$, which is less than 1% of the die size. The converter is able to provide a maximum load current of 250 mA at an input voltage ranging from 2.5 to 4.5 V. The output voltage can be externally set from 4 to 8 V with a resistor divider. Digital soft-start, cycle-by-cycle current limit and thermal shutdown are also integrated in this circuit in order to improve the reliability of the boost converter. The test circuit of the proposed boost DC-DC converter is shown in Fig. 12. The component values and output voltage are shown in Table 2.

Figure 13 presents the experimental results of the proposed boost DC-DC converter under the condition of $V_{\rm IN}$ $=$ 3.3 V, $V_{\rm O}$ $=$ 4.6 V and $I_{\rm O}$ $=$ 250 mA (maximum load). The converter works in continuous conduction mode (CCM) and the output voltage ripple is only 35 mV.

Figure 14 presents the experimental results of the proposed boost DC-DC converter under the condition of $V_{\rm IN}$ $=$ 3.3 V, $V_{\rm O}$ $=$ 4.6 V and $I_{\rm O}$ $=$ 30 mA. The converter works in discontinuous conduction mode (DCM) and the ringing appeared at node $V_{\rm LX}$ when both MN and MP are off has effectively been suppressed. The measured waveforms agree with the simulation results and theory analysis perfectly. Furthermore, by carefully designing the DTC circuit, the on time of body diode is only about 15 ns and the duration of reverse inductor current is only about 50 ns owing to the inherent propagation delay in the DTC circuit and power transistors.

Figure 15(a) shows the reference voltage of the proposed boost converter under the condition of $V_{\rm IN}$ $=$ 3.3 V, $V_{\rm O}$ $=$ 4.6 V, $I_{\rm O}$ $=$ 0 mA and $T_{\rm A}$ $=$ $-40$ to 125 ℃. The variation of the reference voltage is only 2.6 mV under a wide range of temperatures.

Figure 15(b) shows the line regulation of the proposed boost converter under the condition of $V_{\rm IN}$ $=$ 2.5-4.5 V, $V_{\rm O}$ $=$ 4.6 V, $I_{\rm O}$ $=$ 5 mA and $T_{\rm A}$ $=$ 25 ℃. The variation of the output voltage is only 1 mV and the line regulation is less than 0.03% under a wide range of input voltages.

Figure 15(c) shows the load regulation of the proposed boost converter under the condition of $V_{\rm IN}$ $=$ 3.3 V, $V_{\rm O}$ $=$ 4.6 V, $I_{\rm O}$ $=$ 0-250 mA and $T_{\rm A}$ $=$ 25 ℃. The variation of the output voltage is only 12 mV and the load regulation is less than 0.3% under a wide range of load currents.

Figure 15(d) shows the power efficiency of the proposed boost converter under the condition of $V_{\rm IN}$ $=$ 3.3 V, $V_{\rm O}$ $=$ 4.6 V, $I_{\rm O}$ $=$ 10-250 mA and $T_{\rm A}$ $=$ 25 ℃. By using the internal synchronous rectification, a maximum power efficiency of 90% is obtained at about 100 mA load current. Also, by improving the switching timing of power transistors with the proposed DTC circuit and anti-ringing circuit, the power efficiency of the boost converter is above 81% under different load currents from 10 to 250 mA. Table 3 shows the performance comparison of the proposed boost DC-DC converter and the EUP2512 under room temperature. From the comparison results, high efficiency is achieved by using the proposed technique.

5. Conclusions

In this paper, a synchronous boost DC-DC converter with proposed DTC circuit and anti-ringing circuit is analyzed and successfully achieved. The DTC circuit provides adaptive dead time control and zero inductor current detection, thus helping in improving the power efficiency by minimizing the shoot-through current loss, the body diode conduction loss, the charge-sharing loss and the reverse inductor current loss. Additionally, the proposed anti-ringing circuit with a DTD cell not only attenuates the EMI noise but also further enhances the power efficiency by suppressing the ringing when the boost converter works in DCM. Experimental results show that the designed boost DC-DC converter achieves high efficiency and low EMI and that it is suitable for portable devices.