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J. Semicond. > 2014, Volume 35 > Issue 7 > 074012

SEMICONDUCTOR DEVICES

Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure

Chen Cao, Bing Zhang, Longsheng Wu, Xin Li and Junfeng Wang

+ Author Affiliations

 Corresponding author: Cao Chen, Email:intercaochen@163.com

DOI: 10.1088/1674-4926/35/7/074012

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Abstract: A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson's equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.

Key words: pinned photodiodepixel designpinch-off voltageanalytical model

In recent years, CMOS image sensors (CIS) have caused widespread interest due to low power consumption, low cost, low noise and high integration density etc., and the advantages could cause CIS to replace the charge coupled device (CCD) gradually and occupy the mainstream image sensor market[1, 2]. The 4-transistor CMOS image pixels using a pinned photodiode (PPD) structure as the photon sensing area further reduce the reset noise, dark current and fixed pattern noise (FPN) of CIS. Simultaneously, the image quality can be compensated by correlated double sampling (CDS) technology[3]. Therefore, the PPD structure is widely used in modern high-performance CIS.

Pinch-off voltage is a key index for PPD pixel design. The lower the pinch-off voltage is, the more easily the N buried layer in PPD reaches full depletion state, then becomes a charge empty well under small reset bias, and is also good for a complete charge transferring from PPD to the floating diffusion node[4]. But if the pinch-off voltage is too low, a decreasing of full well capacity can be caused, and the dynamic range may also be influenced greatly[5]. Therefore, the modeling development of the pinch-off voltage in a PPD could provide a theoretical guidance for evaluating optoelectronics properties in CIS pixels.

However, there is a lack of papers reporting on the modeling research of the pinch-off voltage. According to the study of the relationship between the number of the photon-generated electrons and the electrostatic potential in a PPD structure, Krymiki predicted the pinch-off voltage for the first time[6]. By considering the influences of lateral electric field effect on the barrier regions of small pixel size, Park modified Krymiki's model[7]. The references above both supposed the impurity concentration distribution of the N buried layer in a PPD is uniform, but in fact, the N buried layer doping is generally formed by ion implantation and diffusion at a high temperature atmosphere, and the impurity concentration distribution should be non-uniform due to the impurity compensation. In order to improve the absorption efficiency under long wavelength illumination, the N buried layer extends deeply into the substrate, causing the doping non-uniformly more obviously[8]; if we continue following the traditional pinch-off voltage model, it will make a deviation between a theoretical value and an actual value.

In this paper, a novel pinch-off voltage model is proposed, in which the influences of the N buried layer doping non-uniformly are considered by approximating the upper boundary PN junction for short wavelength absorption as an abrupt junction, while the lower one for long wavelength absorption as a doping slowly varied junction. Test results have verified that the derived model could accurately predict the pinch-off voltage.

Figure 1 shows the basic 4-transistor CMOS image pixel configuration with a PPD structure. It consists of a PPD, a transfer gate (TG), a rest transistor (RST), a source follower (SF) and a row selection transistor (SEL). The PPD is a buried layer structure with at least two ion implant steps, the first is deep N type implant, the second is surface P+ implant. The N buried layer is an area in which photons are absorbed and electron-hole pairs can be excited. The purpose of surface P+ injection is to prevent photon sensing area from touching the Si-SiO2 interface, and eliminate the dark current originating from the interface states and the trapped charges laid in the dielectric layers.

Figure  1.  Basic 4-transistors CMOS image pixel configuration.

The energy band of electrons along x-x' in Fig. 1 is drawn in Fig. 2. When the PPD remain in equilibrium state, the N buried layer has a neutral region as shown in Fig. 2(a), and two PN junctions located at upper and lower boundaries of the N buried layer have a unified Fermi level EF. The neutral region disappears after the pixel reset operation sweeps out all the electrons in the N buried layer as shown in Fig. 2(b), and there's no Fermi level, so the PPD structure achieves full depletion. The difference of the lowest conduction band energy between N barrier region and P-type neutral region is the electrical potential energy which represents the pinch-off voltage, which can be expressed as:

Figure  2.  Energy band of electrons along x-x' in Fig. 1. (a) Equilibrium state. (b) Full depletion state.

EC,NbarrierEC,Pneutral=qVpinned,

(1)

where Vpinned is the pinch-off voltage.

When a semiconductor material is illuminated by a light source with intensity of ${\mathit{\Phi }_{{\rm{i0}}}}$ at the surface, the incoming photons can be absorbed and free electrons if their energy equals or exceeds that of the band gap. The photons' absorption is not linear with photon energy, and is defined by the absorption coefficient α. The energy absorbed at a certain depth x is given by[9]:

${\mathit{\Phi }_{\rm{i}}}\left( x \right) = {\mathit{\Phi }_{{\rm{i0}}}}\exp \left( { - \alpha x} \right).$

(2)

The absorption coefficient is a strongly decreasing function of wavelength as shown in Fig. 3 with silicon material. Therefore, the absorption length $\alpha^{-1}$, defined as the distance at which the intensity of light is reduced to $e^{-1}$ times of the initial value is increased versus wavelength.

Figure  3.  Absorption coefficient of silicon as a function of wavelength[9].

From Fig. 3, it is noted that, for the visible light spectrum response (from 300 to 700 nm), the absorption length varies between 0.01 and 5 μm. That means the width of N type region has to be extended in a PPD structure for effective visible light detecting in the barrier region established by the two boundary PN junctions. The extension leads to an obvious phenomenon of doping non-uniformly introduced by manufacturing processes of the N buried layer. In this case, the upper junction for short wavelength absorption and lower junction for long wavelength absorption located at the boundaries of N region present different characteristics, respectively. Then, it may not be treated as uniform doping concentration everywhere in the whole PPD structure like depicted in Refs. [6, 7].

A PPD can be simplified as the three layer configuration shown in Fig. 4. It consists of an upper junction between the surface P+ implant and the N buried layer, a lower junction between the N buried layer and the P epitaxial layer. Figures 4(a) and 4(b) show the equilibrium state and full depletion state, respectively.

Figure  4.  A simplified three-layer PPD configuration. (a) Equilibrium state. (b) Full depletion state.

As mentioned above, the surface P+ implant must be as shallow as possible and achieve high doping concentration simultaneously in order to obtain high absorption efficiency for short wavelength illumination and eliminate the dark current. So the upper junction of the N buried layer can be approximated by an abrupt junction. As Figure 4(a) shows, by solving the Poisson's equations in the barrier regions with the boundary conditions, the vertical width of the upper junction barrier region which is reverse biased by $V_1$ can be solved out as[10]:

WD1=(Vi1+V1)2εrε0qNP++NNNP+NN,

(3)

where NP+ and NN are the concentrations of acceptor and donor, respectively, NN can be regarded as the maximum doping concentration of the N buried layer; $\varepsilon _{\rm r} \varepsilon _0$ is dielectric constant of silicon material; q is the unit charge; Vi1 represents the built-in voltage in equilibrium state and is given as[10]:

Vi1=k0TqlnNNNP+n2i,

(4)

where $k_0$ is the Boltzmann constant; T is the temperature (the modeling is based on room temperature, 300 K), ni is the concentration of intrinsic carrier at 300 K.

Generally, NP+ is two orders of magnitude higher than NN[11]. Therefore, Equation (3) can be written as:

WD1=Xn1=2εrε0qNN(Vi1+V1).

(5)

The distribution of impurities in the deeply N buried layer is determined by the impurity compensation of the N type implant and P epitaxial, so the doping concentration of the lower junction of the N buried layer is slowly varied with a gradient factor $\sigma _{\rm j}$. As Figure 4(a) shows, the Poisson's equation in the barrier region is given by:

2Vlow(x,y)x2=qσjxεrε0,Xj2Xn2<x<Xj2+Xp2.

(6)

where Vlow (x, y) represents the potential of the whole barrier region. The total numbers of positive and negative space charge in the barrier region are equal, so Xp2 and Xn2 shown in Figure 4(a) should also be equal. Then, leading to the boundary conditions:

Vlow(x,y)x|x,=,Xj2±Xn2=0,

(7)

Vlow(Xj2)=0.

(8)

Therefore, the vertical width of the lower junction barrier region, which is reverse biased by $V_2$, can be solved out as:

WD2=2Xn2=312εrε0(Vi2+V2)qσj.

(9)

Being similar to Eq. (4):

Vi2=k0TqlnNDminNPepin2i,

(10)

where $N_{{\rm D min}}$ and $N_{\rm P-epi}$ respectively represent the concentrations of donor and acceptor in the infinitely small region around the metallurgical junction. Due to the characteristic of the doping slowly varied junction, $N_{{\rm D min}}$ can be easily equal to $N_{\rm P-epi}$. Then Equation (10) can be written as:

Vi2=k0TqlnN2Pepin2i.

(11)

When the N buried layer is reset to the full depletion state, as Figure 4(b) shows, the barrier regions previous separately formed by the upper and lower boundary junctions of the N buried layer have been merged, and the bias on the new barrier region is pinned by pinch-off voltage Vpinned, as the following equation depicts:

Xd=Xn1+Xn2.

(12)

Combining Eqs. (4), (5), (9), (11), and (12), we can know that:

Xd=2εrε0qNN(k0TqlnNNNP+n2i+Vpinned)+12312εrε0(k0TqlnN2Pepin2i+Vpinned)(qσj)1.

(13)

By taking account of the influences of lateral electric field effect for small pixel size[7], the equation above can be written as:

Xd=[2εrε0qNNβ(L0LL0)n]A+12[312εrε0qσjβ(L0LL0)n]B,

(14)

where

$ A= {\frac{k_0 T}{q} {\ln \frac{N_{\rm N} N_{\rm P+} }{n_{\rm i} ^2}}+V_{\rm pinned} }, $

$ B= {\frac{k_0 T}{q}{\ln \frac{N_{\rm P-epi} ^2}{n_{\rm i}^2}}+V_{\rm pinned} }, $

where $L_0$ and L represent the lateral length of the PPD with and without lateral electric field effect, respectively; $\beta$ is a constant that can be tested by experiment, and n is the degree of the lateral electric field effect.

From Eq. (14), it is noted that

Vpinned=f(NN,Xd,σj,C),

(15)

where C is a constant determined by the parameters of pixel structure and wafer materials. The $\sigma_{\rm j}$ is the item which can reflect the non-uniform doping concentration distribution. Equation (15) indicates that the pinch-off voltage can be determined only by the process flow of N region for a certain PPD pixel.

For the verification of the doping distribution involved in this paper, a 3D PPD pixel structure with TG tied to a floating diffusion (FD) node is grown by Synopsys TCAD process simulation as shown in Fig. 5(a). Synopsys TCAD is a widely recognized process and device simulator[12]. The dimensions of the structure are 2.5 × 2.5 × 5 μm3 with TG gate length of 0.35 μm. The N buried layer is implanted by arsenic impurity with a dose of 5 × 1012 cm-2 and an energy of 150 keV, where the width of N region is approximately 1 μm for the visible light spectrum response. After N region is achieved, a surface P+ implant by boron impurity with a dose of 8 × 1012 cm-2 and an energy of 5 keV is introduced. The whole device is grown on a P type epitaxial layer with a concentration of 1015 cm-3. The cross section of the 3D pixel along the x axis is shown in Fig. 5(b).

Figure  5.  (a) 3D PPD pixel model. (b) Cross section along x axis.

Figure 6 shows the non-uniform doping concentration distributions near the upper and lower boundary junctions of the N buried layer, respectively, where ND and NA represent the arsenic and boron doping concentrations, respectively. As shown in Fig. 6(a), the curves of ND and NA are drawn steeply since the surface P+ implant, and are gentle as going deep into the N region due to the impurity compensation. As shown in Fig. 6(b), it is noted that the doping concentration distributions are much more moderate than the upper junction.

Figure  6.  Boundaries doping concentration of N buried layer. (a) Upper junction. (b) Lower junction.

The doping concentration determined by the impurity compensation can be given as:

NDNA=σj(xxj),

(16)

where xj is the depth of the metallurgical junction, the gradient factor $\sigma _{\rm j}$ can be clarified as the slope of the ND -NA curve at the location of PN metallurgical junction, which are the regions marked by dashed circles in Figs. 6(a) and 6(b). The $\sigma _{\rm j}$ can be approximately read by 5.4 × 1023 cm-4 and 4.0 × 1020 cm-4 of the upper and lower boundary junctions, respectively. Since the difference of the doping gradients is more than 3 orders of magnitude, the upper and lower boundary junctions of the N buried layer can be regarded as an abrupt and a doping slow variation junction, respectively.

For the verification of the derived pinch-off voltage model, pixels with PPD structures were fabricated by the DSM CMOS image sensor dedicated technology. The pixel size is 3 × 3 μm2. The epitaxial layer with the concentration of 1015 cm-3 was grown on the high doping (1018 cm-3) substrate. The surface P+ region of the PPD was fabricated by the implantation with a dose of 8 × 1012 cm-2. The N type region of the PPD was fabricated by the implantations with various different doses and energies which are listed in Tables 1 and 2. Based on Eqs. (17) and (18) below, the parameters NN and $\sigma _{\rm j}$ which are needed for the pinch-off voltage modeling can be extracted by C-V measurements[10]. The parameter Xd can be measured by using the method of chemical reagent development in which the p, n-type region can be easily distinguished on the cross section of the cutting test chip.

d(1C2)dV=2C3dCdV=2A2εrε0qNN,

(17)

1C3=12(VDV)A3ε2rε20qσj.

(18)
Table  1.  Different implant doses with energy of 150 keV.
DownLoad: CSV  | Show Table
Table  2.  Different implant energies with dose of 5 × 1012 cm-2.
DownLoad: CSV  | Show Table

In addition, the constant $\beta $ and degree n are set to 1.3 and 1.5, respectively due to the experimental data from Ref. [7].

The test pattern for measuring the pinch-off voltage can be similar to a structure of JFET, which is shown in Fig. 7(a). As the VD increases, due to the $\Delta V_{\rm D}$ voltage drop, the current ID which flows through the N region can be tested by the N$^+$ contact until the VD is higher than the pinch-off voltage of the PPD. So the maximum voltage at which the current can flow should be the pinch-off voltage as depicted in Fig. 7(b). For the different values of $\Delta V_{\rm D}$, only one unified pinch-off voltage can be measured according to the principle of JFET's transfer characteristics[13].

Figure  7.  (a) Test pattern for measuring the pinch-off voltage. (b) The maximum VD at which ID can flow represents the pinch-off voltage.

The test results compared to the calculation values of both the traditional and the derived pinch-off voltage models are shown in Figs. 8(a) and 8(b) under various implant conditions. Note that the derived model shows a good agreement with the measurements. The pinch-off voltage presents a linear increase versus both implant dose and energy of the N buried layer. The values of the traditional model under low dose or low energy implantation can fit to both the derived model values and test results. However, with the above implant conditions growing up, the traditional model shows a large deviation from the measurements. It can be explained that, without taking account of the gradient attenuation doping of the N buried layer in traditional model, a stronger bias must be supplied to exhaust the N neutral region, causing an increase of the pinch-off voltage. The deeper the N buried layer extends by increasing implant dose and energy, the more obviously the gradient doping shows, leading to a larger growth of the gap between the traditional model and the derived model as Figure 8 shows. Therefore, the traditional model is only suitable for a very limited range of implant conditions, while the derived model can be suitable more widely.

Figure  8.  Pinch-off voltage versus various implant conditions of N buried layer. (a) Different doses. (b) Different energies.

After the implant dose reaches 6 × 1012 cm-2 or the energy reaches 175 keV, the values of the derived model present slightly lower (approximately 10%) than the measurements as shown in Fig. 8. It can be explained that the maximum concentration under the implant conditions above can be compared to the surface P+ implant, so the width of the vertical barrier region in P+ layer cannot be ignored anymore, in this case, Equation (5) which emerged during the modeling in Section 3.2 should be revised as:

Xn1=NP+NN+NP+WD1=NP+NN+NP+(Vi1+V1)2εrε0q1NP+NN.

(19)

So the derived pinch-off voltage model should be revised as:

Vpinned=f(NN,NP+,Xd,σj,C).

(20)

From Eq. (19), it can be noted that a part width of the barrier region described in the former pinch-off voltage model is occupied by the P+ layer, resulting in a higher bias supply to reach the original barrier width. So the pinch-off voltage is raised due to the influence of the acceptor concentration in P+ layer as Equation (20) depicted.

We developed an analytical model for predicting the pinch-off voltage for CMOS image pixels with a pinned photodiode structure, which can feature the influences by gradient doping in the N buried layer. Based on analysis of the different characteristics of two boundary PN junctions located in the region for particular spectrum response in a pinned photodiode, the relationships between the pinch-off voltage and the corresponding process parameters are derived. The novel model is verified by test results, and is proved to be more precise under wide implant conditions than the traditional model.



[1]
Fossum E R. CMOS image sensors: electronic camera-on-a-chip. IEEE Trans Electron Devices, 1997, 44: 1689 doi: 10.1109/16.628824
[2]
Lule T, Benthien S, Keller H, et al. Sensitivity of CMOS based imagers and scaling perspectives. IEEE Trans Electron Devices, 2000, 47: 2110 doi: 10.1109/16.877173
[3]
Inoue I, Tanaka N, Yamashita H, et al. Low leakage current and Low operating voltage buried photodiode for a CMOS imager. IEEE Trans Electron Devices, 2003, 50: 43 doi: 10.1109/TED.2002.807525
[4]
Li Binqiao, Yu Junting, Xu Jiangtao, et al. An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor. Journal of Semiconductors, 2010, 31(7): 074010 doi: 10.1088/1674-4926/31/7/074010
[5]
Bigas M, Cabruja E, Forest J, et al. Review of CMOS image sensors. Microelectron J, 2006, 37(5): 433 doi: 10.1016/j.mejo.2005.07.002
[6]
Krymski A I, Bock N E, Tu N, et al. Estimates for Scaling of Pinned Photodiodes. IEEE Workshop on CCD and Advanced Image Sensors, 2005: 60 http://m.alexima.com/pub/Scaling_Pinned.pdf
[7]
Park S, Uh H. The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors. Microelectron J, 2009, 40: 137 doi: 10.1016/j.mejo.2008.06.071
[8]
Zou Jijun, Chang Benkang, Yang Zhi. Theoretical calculation of quantum yield for exponential-doping GaAs photocathodes. Acta Phys Sin, 2007, 56: 2992(in Chinese) http://wulixb.iphy.ac.cn/EN/article/downloadArticleFile.do?attachType=PDF&id=12953
[9]
Adam G. Investigation of 4T CMOS image sensor design and the effects of radiation damage. PhM Dissertation, University of Surrey, UK, 2010: 5
[10]
Liu Enke, Zhu Bingsheng, Luo Jinsheng. Semiconductor physics. Beijing: Publishing House of Electronics Industry, 2008(in Chinese)
[11]
Lee P P, Guidash R M, Stevens E G, et al. Active pixel sensor integrated with a pinned photodiode. USA Patent, No. 5625210, 1997
[12]
Liang Bin, Chen Shuming, Liu Biwei. Using 3D TCAD simulation to study charge collection of a p-n junction in a 0.18μm bulk process. Journal of Semiconductors, 2008, 29(9): 1692 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=08011003&flag=1
[13]
Simon M, Kwok K. Physics of semiconductor devices. Xi'an: Xi'an Jiaotong University Press, 2008(in Chinese)
Fig. 1.  Basic 4-transistors CMOS image pixel configuration.

Fig. 2.  Energy band of electrons along x-x' in Fig. 1. (a) Equilibrium state. (b) Full depletion state.

Fig. 3.  Absorption coefficient of silicon as a function of wavelength[9].

Fig. 4.  A simplified three-layer PPD configuration. (a) Equilibrium state. (b) Full depletion state.

Fig. 5.  (a) 3D PPD pixel model. (b) Cross section along x axis.

Fig. 6.  Boundaries doping concentration of N buried layer. (a) Upper junction. (b) Lower junction.

Fig. 7.  (a) Test pattern for measuring the pinch-off voltage. (b) The maximum VD at which ID can flow represents the pinch-off voltage.

Fig. 8.  Pinch-off voltage versus various implant conditions of N buried layer. (a) Different doses. (b) Different energies.

Table 1.   Different implant doses with energy of 150 keV.

Table 2.   Different implant energies with dose of 5 × 1012 cm-2.

[1]
Fossum E R. CMOS image sensors: electronic camera-on-a-chip. IEEE Trans Electron Devices, 1997, 44: 1689 doi: 10.1109/16.628824
[2]
Lule T, Benthien S, Keller H, et al. Sensitivity of CMOS based imagers and scaling perspectives. IEEE Trans Electron Devices, 2000, 47: 2110 doi: 10.1109/16.877173
[3]
Inoue I, Tanaka N, Yamashita H, et al. Low leakage current and Low operating voltage buried photodiode for a CMOS imager. IEEE Trans Electron Devices, 2003, 50: 43 doi: 10.1109/TED.2002.807525
[4]
Li Binqiao, Yu Junting, Xu Jiangtao, et al. An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor. Journal of Semiconductors, 2010, 31(7): 074010 doi: 10.1088/1674-4926/31/7/074010
[5]
Bigas M, Cabruja E, Forest J, et al. Review of CMOS image sensors. Microelectron J, 2006, 37(5): 433 doi: 10.1016/j.mejo.2005.07.002
[6]
Krymski A I, Bock N E, Tu N, et al. Estimates for Scaling of Pinned Photodiodes. IEEE Workshop on CCD and Advanced Image Sensors, 2005: 60 http://m.alexima.com/pub/Scaling_Pinned.pdf
[7]
Park S, Uh H. The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors. Microelectron J, 2009, 40: 137 doi: 10.1016/j.mejo.2008.06.071
[8]
Zou Jijun, Chang Benkang, Yang Zhi. Theoretical calculation of quantum yield for exponential-doping GaAs photocathodes. Acta Phys Sin, 2007, 56: 2992(in Chinese) http://wulixb.iphy.ac.cn/EN/article/downloadArticleFile.do?attachType=PDF&id=12953
[9]
Adam G. Investigation of 4T CMOS image sensor design and the effects of radiation damage. PhM Dissertation, University of Surrey, UK, 2010: 5
[10]
Liu Enke, Zhu Bingsheng, Luo Jinsheng. Semiconductor physics. Beijing: Publishing House of Electronics Industry, 2008(in Chinese)
[11]
Lee P P, Guidash R M, Stevens E G, et al. Active pixel sensor integrated with a pinned photodiode. USA Patent, No. 5625210, 1997
[12]
Liang Bin, Chen Shuming, Liu Biwei. Using 3D TCAD simulation to study charge collection of a p-n junction in a 0.18μm bulk process. Journal of Semiconductors, 2008, 29(9): 1692 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=08011003&flag=1
[13]
Simon M, Kwok K. Physics of semiconductor devices. Xi'an: Xi'an Jiaotong University Press, 2008(in Chinese)
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Chinese Journal of Semiconductors , 2005, 26(12): 2303-2308.

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    Chen Cao, Bing Zhang, Longsheng Wu, Xin Li, Junfeng Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. Journal of Semiconductors, 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012
    C Cao, B Zhang, L S Wu, X Li, J F Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. J. Semicond., 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012.
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    Received: 29 November 2013 Revised: 20 January 2014 Online: Published: 01 July 2014

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      Chen Cao, Bing Zhang, Longsheng Wu, Xin Li, Junfeng Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. Journal of Semiconductors, 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012 ****C Cao, B Zhang, L S Wu, X Li, J F Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. J. Semicond., 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012.
      Citation:
      Chen Cao, Bing Zhang, Longsheng Wu, Xin Li, Junfeng Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. Journal of Semiconductors, 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012 ****
      C Cao, B Zhang, L S Wu, X Li, J F Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure[J]. J. Semicond., 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012.

      Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure

      DOI: 10.1088/1674-4926/35/7/074012
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      • Corresponding author: Cao Chen, Email:intercaochen@163.com
      • Received Date: 2013-11-29
      • Revised Date: 2014-01-20
      • Published Date: 2014-07-01

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