Fig. 1.
The structure chart of an NMOSFET.
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| Citation: |
Shangqing Ren, Bo Tang, Hao Xu, Weichun Luo, Zhaoyun Tang, Yefeng Xu, Jing Xu, Dahai Wang, Junfeng Li, Jiang Yan, Chao Zhao, Dapeng Chen, Tianchun Ye, Wenwu Wang. Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process[J]. Journal of Semiconductors, 2015, 36(1): 014007. doi: 10.1088/1674-4926/36/1/014007
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S Q Ren, B Tang, H Xu, W C Luo, Z Y Tang, Y F Xu, J Xu, D H Wang, J F Li, J Yan, C Zhao, D P Chen, T C Ye, W W Wang. Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process[J]. J. Semicond., 2015, 36(1): 014007. doi: 10.1088/1674-4926/36/1/014007.
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Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process
DOI: 10.1088/1674-4926/36/1/014007
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Abstract
Positive bias temperature instability (PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 eV, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift. -
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