Abstract: The analytical model of voltage-controlled MOS capacitance of tapered through silicon via (TSV) is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG for two-wire transmission lines are revised. With the adoption of MOS capacitance model and the revised RLCG analytical equations, a transmission line-type electrical model for tapered TSV is proposed finally. All the proposed models are validated by simulation tools, and a good correlation is obtained between the proposed models and simulations up to 100 GHz. With the proposed model, both the semiconductor phenomenon and frequency-dependent behavior of tapered TSV can be fully captured at high frequency, and the performance of tapered TSV can be evaluated accurately and conveniently prior to 3D IC design.

Key words: 3D IC, TSV, TSV electrical model, MOS effect, transmission line