Fig. 1.
Schematic of the proposed voltage reference.
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| Citation: |
Jihai Duan, Dongyu Deng, Weilin Xu, Baolin Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. Journal of Semiconductors, 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006
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J H Duan, D Y Deng, W L Xu, B L Wei. An extremely low power voltage reference with high PSRR for power-aware ASICs[J]. J. Semicond., 2015, 36(9): 095006. doi: 10.1088/1674-4926/36/9/095006.
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An extremely low power voltage reference with high PSRR for power-aware ASICs
DOI: 10.1088/1674-4926/36/9/095006
More Information
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Abstract
An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs. -
References
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Proportional views
