J. Semicond. > 2016, Volume 37 > Issue 5 > 054006
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SEMICONDUCTOR DEVICES

An LDMOS with large SOA and low specific on-resistance

Wenfang Du, Xinjiang Lyu and Xingbi Chen

+ Author Affiliations

 Corresponding author: Corresponding author. Email: xbchen@uestc.edu.cn

DOI: 10.1088/1674-4926/37/5/054006

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Abstract: An LDMOS with nearly rectangular-shape safe operation area (SOA) and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be lowered down to 74.7 mΩ·cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ionization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large VGS is obtained and snap-back is suppressed as well.

Key words: LDMOS, safe operation area (SOA), snap-back, split gate



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Fig1.  Schematic diagram of the proposed structure.

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Fig2.  Comparison of the $I$-$V$ curves between the entire proposed device (solid lines) and the n-MOS part of the proposed device (dashed lines).

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Fig4.  Profiles of electric field along the surface of the p-top region.

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Fig5.  Comparison of the maximum impact ionization integral.

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Fig6.  Comparison of the electron profile of the surface of the n-well at $V_{\rm GS}$ $=$ 9 V and $V_{\rm DS}$ $=$ 100 V.

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Fig7.  (Color online) Comparison of $R_{\rm on,\rm sp}$ versus $V_{\rm B}$ for different technologies.

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Fig8.  (Color online) The process steps of the fabrication of the proposed device: (a) implantation of p-bury layer into n-type substrate; (b) implantations of p-well and n-well; (c) growth of gate oxide and deposition of poly-silicon layer; (d) implantations of p-top layer and p$^{+}$-gate; (e) n$^{+}$/p$^{+}$ implantation; (f) metallization.

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Table 1.   List of design parameters

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    Received: 07 September 2015 Revised: Online: Published: 01 May 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(5): 054006
      Wenfang Du, Xinjiang Lyu, Xingbi Chen. An LDMOS with large SOA and low specific on-resistance[J]. Journal of Semiconductors, 2016, 37(5): 054006. doi: 10.1088/1674-4926/37/5/054006 ****W F Du, X Lyu, X B Chen. An LDMOS with large SOA and low specific on-resistance[J]. J. Semicond., 2016, 37(5): 054006. doi: 10.1088/1674-4926/37/5/054006.
      Citation:
      Wenfang Du, Xinjiang Lyu, Xingbi Chen. An LDMOS with large SOA and low specific on-resistance[J]. Journal of Semiconductors, 2016, 37(5): 054006. doi: 10.1088/1674-4926/37/5/054006 ****
      W F Du, X Lyu, X B Chen. An LDMOS with large SOA and low specific on-resistance[J]. J. Semicond., 2016, 37(5): 054006. doi: 10.1088/1674-4926/37/5/054006.
      shu

      An LDMOS with large SOA and low specific on-resistance

      DOI: 10.1088/1674-4926/37/5/054006

      • State Key Laboratory of Electronic Thin Films and Integrated Devices of China, University of Electronic Science and Technology of China, Chengdu 610054, China

      Funds:

      Project supported in part by the National Natural Science Foundation of China (No. 51237001).

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      • Corresponding author: Corresponding author. Email: xbchen@uestc.edu.cn
      • Received Date: 2015-09-07
      • Accepted Date: 2015-11-05
      • Published Date: 2016-01-25

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