1. Introduction

For the high-voltage power laterally double diffused metal oxide semiconductor field effect transistor (LDMOS),research attention has been increasingly placed on the trade-off between breakdown voltage ($V_{\rm B})$ and specific on-resistance ($R_{\rm on,\rm sp}) ^{^{[1, 2]}. Recently,an n-type LDMOS by using a split gate was proposed to induce an additional electron accumulation layer,which obtains an ultra-low $R_{\rm on,\rm sp}$ with a given $V_{\rm B}{}^{^{[3, 4]}. However,like other n-type high-voltage LDMOS,there exists a snap-back in $I$-$V$ curves or earlier breakdown under high-voltage and high-current condition,which reduces the survivability during the switching operation^[5]. It is caused by the fact that a large number of electrons are introduced by current,which enhance the electric field near the drain^[6]. As a result,extra electron-hole pairs are generated by impact ionization and holes are driven into the p-type source-body region by the electric field. Once the hole current is large enough to turn on the parasitic n$^{+}$-source/p-source-body/n-drift BJT,the snap-back occurs in $I$-$V$ curves^{[5, 6, 7]}. Prior arts increase the doping concentration of the source-body region to suppress the turn-on of the parasitic npn BJT^[8]. However,the high electric field around the drain still exists,which would cause earlier breakdown under high-voltage and high-current condition.

In this work,a novel method by using both electrons and holes as the majority carriers for conduction under the high-voltage and high-current conditions^[9] is employed to the LDMOS with a split gate. The high electric field is eliminated by the charge compensation of the majority electrons and holes,which weakened the impact ionization and suppresses the snap-back. Therefore,a large SOA and low $R_{\rm on,\rm sp}$ are obtained in the proposed device.

2. Device structure and description

Figure1 shows the schematic view of the proposed structure,which includes an n-type LDMOS and a p-MOS. The entire structure has three external terminals (S,G,and D),which serves as an n-LDMOS. The voltage-sustaining region of the device consists of p-top,n-well,p-bury and n-substrate layers. The p-top layer is implemented on the gate oxide,forming a split gate. The electrode G$_{1}$ of the split gate is connected to one plate of Capacitor C$_{0}$,where the other plate of C$_{0}$ is connected to source electrode S.

The on-state operation of the proposed device is explained as below. During the on-state,when $V_{\rm GS}$ > $V_{\rm th}$($n$),$V_{\rm DS}$ $\approx$ 0,the initial voltage on the capacitor C$_{0}$ denoted as $V_{\rm C0}$,has a constant positive value. It means the potential of the p-top is higher than that of the surface of the n-drift region. Thus,electrons flowing from the n-channel into the drift region are accumulated beneath the split gate oxide. As a result,$R_{\rm on,\rm sp}$ is much lower than that of a conventional LDMOS without an accumulation layer^{[3, 4]}. On the other hand,in the path of electrons from source electrode S to drain electrode D,there is a negative voltage drop $V_{\rm GpD}$ across the n$^{+}$-region connected with the gate of the p-MOS $G_{\rm p}$ and n$^{+}$-drain region due to the presence of the parasitic resistance between them. When the value of $V_{\rm GpD}$ is lower than the threshold voltage of the p-MOS,the p-MOS is turned on. The hole current flows from the p$^{+}$-region connected with electrode D into the split p-gate through the p-channel,the p-top region at the right end,the diode d$_{2}$ and p$^{+}$-regions. At the end,it flows into source electrode S through a Zener diode d$_{1}$,which has a clamping voltage of $V_{\rm C0}$. The holes flowing in the p-top region compensate with the electrons in the n-drift region to some extent,alleviating the crowding of the electric field lines around the drain region^[9]. As a result,the local impact ionization is suppressed and the on-state breakdown voltage is increased significantly.

During the high-voltage and high-current state,holes and electrons are isolated by the gate oxide and flow in the split gate and n-well,respectively. Thus,the proposed device is conducted with both holes and electrons as majority carriers.

In the off-state with $V_{\rm GS}$ $=$ 0 and $V_{\rm DS}>$ 0,there is no hole current in the p-top. Due to that there is no electron current flowing in the drift region,$V_{\rm GpD}$ is close to 0 and the p-MOS is turned off. The p-top,n-well and p-bury layers are fully depleted to sustain the high voltage.

The diodes d$_{2}$ and d$_{3}$ in Figure1 prevent the holes from flowing out of the split gate in the on-state$^{ ^[3]. An integrated power supply technology^[4] or a gate-driver circuit can be utilized to charge capacitor C$_{0}$ at start up^[3].

3. Simulation results and analyses

The electric characteristics of the proposed structure with off-state breakdown voltage as 600 V are obtained by using the simulation tool MEDICI. Models of CONMOB,FLDMOB,SRFMOB,SRH and IMPACT.I are used in the simulations. The design parameters of the structure are listed in Table1.

To explore the effect of the actively introduced holes,the $I$-$V$ curves of the proposed device are compared with that of the conventional structure without p-MOS. As shown in Figure2,the electric SOA of the proposed device is much wider and higher than that of the structure without p-MOS. For the structure without p-MOS,a snap-back can be observed before $V_{\rm DS}$ reaches 350 V when $V_{\rm GS} >$ 5 V. While for the proposed structure,the on-state breakdown voltages are above 450 V. The reason for this improvement is explained as below. When there are only majority electrons for conduction,the electric field of the voltage-sustaining region is redistributed and most of $V_{\rm DS}$ drops across the right part of the voltage-sustaining region,as shown in Figures 3. A peak of the surface electric field occurs at the p-top/n$^{+}$ junction in the p-top region,which does not exist in the non-current case,as shown in Figure4. With increasing of $V_{\rm DS}$,the peak of electric field is strengthened,as well as the impact ionization. As a result,the device would be broken down around the p-top/n$^{+}$ junction at $V_{\rm DS}$ with a far smaller value than 600 V. When there are both majority electrons and majority holes for conduction in the high-voltage and high-current state,the electric field profile is optimized and the peak of the electric field is decreased,as shown in Figures 3 and 4. Thus,the on-state breakdown voltage of the proposed device is improved in comparison with the structure without p-MOS. The maximum impact ionization integrals versus $V_{\rm DS}$ of the proposed device and the structure without p-MOS are given in Figure5. It can be seen that the proposed device has a better reliability in the high-voltage and high-current state over the structure without p-MOS.

The higher SOA of the proposed device is attributed to the introduced hole current and the increase in the electron current $I_{\rm e}$,e.g. $I_{\rm e}$ of the proposed device and the structure without p-MOS are 4 × 10$^{-4}$ and 1 × 10$^{-4}$ A/$\mu$m at $V_{\rm GS}$ $=$ 11 V and $V_{\rm DS}$ $=$ 100 V,respectively. In a high-voltage n-LDMOS,the electron current is limited by the saturation of electron velocity^[10]. Due to that the compensation between holes and electrons decreases the maximum electric field in the n-well,the value of the $V_{\rm DS}$ of the proposed device making electron velocity saturated is increased in comparison with the structure without p-MOS. As a result,the saturation electron current of the proposed device is greater than that of the structure without p-MOS at high $V_{\rm DS}$. It is interesting that the electron accumulation layer underneath the gate oxide still exists in the proposed device under high-voltage and high-current condition,while in the structure without p-MOS,the accumulation layer is terminated by the depleted region in the n-well region when $V_{\rm DS}>$ 10 V. Figure6 shows the profile of the electrons near the surface of the n-well region at $V_{\rm GS}$ $=$ 9 V and $V_{\rm DS}$ $=$ 100 V. The continuous accumulation layer provides a smoother path for the electrons and also contributes to the high electron current of the proposed device.

In the on-state,there is an electron accumulation layer of the proposed device. The value of the accumulated electron density is dependent on the value of $V_{\rm G1S}$/$t_{\rm ox}$^[3]. For example,with $V_{\rm GS}$ $=$ 9 V,$V_{\rm G1S}$ $=$ 9 V and $V_{\rm DS}$ $=$ 0.1 V,the accumulated electron density is 5.75 × 10$^{12}$ cm$^{-2}$. $R_{\rm on,\rm sp}$ is obtained as 75.8 m$\upOmega$$\cdot$cm$^{2}$. $R_{\rm on,\rm sp}$ of the proposed device is higher than that of the structure without p-MOS due to the lack of the accumulation layer between the two n$^{+}$-regions in the electron current path of the proposed device. However,the $R_{\rm on,\rm sp}$ of the proposed device is still smaller than that of the conventional devices without the accumulation layer,as shown in Figure7.

4. Discussions and conclusions

The key process steps of fabrication of the proposed device are given in Figure8. This technology is compatible with the conventional CMOS technology. As shown in Figure8,the p-top gate can be implemented by depositing a poly-silicon layer,and then recrystallized using the techniques of encapsulated annealing and excimer laser annealing (ELA) ^[16]. In the proposed device,the diodes d$_{1}$,d$_{2}$,and d$_{3}$ can be easily integrated on-chip. The capacitor C1 can be an external one as discussed in Reference ^[4]. The interconnections can be realized by the process of multilayer metal layers,which is very common in the conventional CMOS process. The p-MOS can be implemented in the un-depleted n-substrate region without extra area cost.

In conclusion,a LDMOS with a wide SOA and low specific on-resistance is proposed in this paper. The low specific on-resistance is due to a split gate forming an accumulation layer for conduction. In the state of high-voltage and high-current,by conducting with both types of majority carriers,the maximum electric field is reduced in comparison with the conventional device conducting with unipolar majority carriers. As a result,a higher on-state breakdown voltage and a larger saturation drain-to-source current are obtained.