Measurement of charge transfer potential barrier in pinned photodiode CMOSimage sensors

Chen Cao; Bing Zhang; Junfeng Wang; Longsheng Wu

doi:10.1088/1674-4926/37/5/054007

J. Semicond. > 2016, Volume 37 > Issue 5 > 054007

SEMICONDUCTOR DEVICES

Measurement of charge transfer potential barrier in pinned photodiode CMOSimage sensors

Chen Cao, Bing Zhang, Junfeng Wang and Longsheng Wu

+ Author Affiliations

DOI: 10.1088/1674-4926/37/5/054007

Abstract: The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices.

Key words: CMOS image sensors (CIS), pinned photodiode (PPD), charge transfer potential barrier (CTPB), photoresponse curve

References

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图1. (Color online) Schematic cross-sectional diagram of the PPD and the TG in 4T-pixel.

Fig.1

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图2. Simplified energy band diagram through the section A-A' indicated in Figure 1 under both states of P$^{+}$-type in the PPD-TG overlapped area (a) accumulated and (b) depleted. $E_{\rm C}$, $E_{\rm V}$ and $E_{\rm F}$ represent the conduction band, valence band and Fermi energy level, respectively. The mark “Accu." and “Depl." represent the states of accumulated and depleted, respectively. }

Fig.2

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图3. Simplified energy band diagram through the section A-A' indicated in Figure 1 under both states of P$^{+}$-type in the PPD-TG overlapped area (a) accumulated and (b) depleted. $E_{\rm C}$, $E_{\rm V}$ and $E_{\rm F}$ represent the conduction band, valence band and Fermi energy level, respectively. The mark “Accu." and “Depl." represent the states of accumulated and depleted, respectively. }

Fig.3

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. (Color online) Simplified electrostatic potential diagram of the charge transfer path for three typical districts as the collected charge increase in the PPD. (I) When qN/C_PPD＜b: almost no charge transfer. (II) When qN/C_PPD is close enough to ＜b: thermionic emission. (III) When qN/C_PPD＞b: meaningful charge transfer.TG-OFF and TG-INV are the TG channel potential with the states of TG “OFF" and “ON", respectively.

Fig.4

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. (Color online) Qualitative photoresponse curve with the identified three charge transfer districts depicted in Figure 3, along with the corresponding diagram of the proposed CTPB measurement method.

Fig.5

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图6. Micrograph of the prototype CIS chip with an array of 160×160 PPD-pixels.

Fig.6

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图7. Photograph of the experimental environment for the CTPB measurement.

Fig.7

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图8. (Color online) Photoresponse curves and the extracted CTPB-induced residual signals under light intensities of (a) 0, (b) 10, (c) 100 and (d) 1000 lux, respectively. The blue and the red curves represent the measured curve and the lift-shifted curve, respectively. The output signal is directly evaluated as a unit of e$^{-}$ by dividing the \textit{CG} (0.35DN/e$^{-})$ from the measured DN value.

Fig.8

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Received: 11 September 2015 Revised: Online: Published: 01 May 2016

The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices.

Measurement of charge transfer potential barrier in pinned photodiode CMOSimage sensors

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