J. Semicond. > 2016, Volume 37 > Issue 9 > 094003
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SEMICONDUCTOR DEVICES

Vertical-dual-source tunnel FETs with steeper subthreshold swing

Zhi Jiang, Yiqi Zhuang, Cong Li, Ping Wang and Yuqi Liu

+ Author Affiliations

 Corresponding author: Jiang Zhi,zjiang@xidian.edu.cn

DOI: 10.1088/1674-4926/37/9/094003

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Abstract: In order to improve the drive current and subthreshold swing (SS), a novel vertical-dual-source tunneling field-effect transistor (VDSTFET) device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 μA at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 fA, an improved average subthreshold swing of 14 mV/dec, and a minimum point slope of 4 mV/dec.

Key words: dual source regions and U-shape-gate tunneling field-effect transistor, subthreshold swing, band-to-band tunneling, on-state current



[1]
Rawat G, Kumar S, Goel E, et al. Analytical modeling of subthreshold current and subthreshold swing of Gaussian doped strained-Si-on-insulator MOSFETs. Journal of Semiconductors, 2014, 35(8): 084001 doi: 10.1088/1674-4926/35/8/084001
[2]
Jiang Zhi, Zhuang Yiqi, Li Cong, et al. Drive current enhancement in TFET by dual source region. J Electric Comput Eng, 2015, 10(1): 1155 http://cn.bing.com/academic/profile?id=1602678720&encoded=0&v=paper_preview&mkt=zh-cn
[3]
Li Cong, Zhuang Yiqi, Wang Ping, et al. A new analytical model for junctionless cylindrical surrounding-gate MOSFETs. IEEE International Conference on Electron Devices and Solid-State {Circuits, 2015, 117(5) http://cn.bing.com/academic/profile?id=1999793054&encoded=0&v=paper_preview&mkt=zh-cn
[4]
Li Cong, Zhuang Yiqi, Zhang Li. A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs. Chin Phys B, 2014, 3(5): 038502 http://cn.bing.com/academic/profile?id=2250506748&encoded=0&v=paper_preview&mkt=zh-cn
[5]
Lattanzio L, De Michielis L, Ionescu A M. The electron-hole bilayer tunnel FET. Solid-State Electron, 2012, 2012(74): 85 http://cn.bing.com/academic/profile?id=2070989338&encoded=0&v=paper_preview&mkt=zh-cn
[6]
Verhulst A S, Leonelli D, Rooyackers R, et al. Drain voltage dependent analytical model of tunnel field-effect transistors. J Appl Phys, 2012, 110(2): 024510 http://cn.bing.com/academic/profile?id=2070580334&encoded=0&v=paper_preview&mkt=zh-cn
[7]
Tiwari P K, Saramekala K, Dubey S, et al. Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates. Journal of Semiconductors, 2014, 35(10): 104002 doi: 10.1088/1674-4926/35/10/104002
[8]
Richter S, Blaeser S, Trellenkamp S. SiGe on SOl nanowire array TFETs with homo- and heterostructure tunnel junctions. Ultimate Integration on Silicon (ULIS), 2013, 6523482: 25 http://cn.bing.com/academic/profile?id=2206270344&encoded=0&v=paper_preview&mkt=zh-cn
[9]
Guo Pengfei, Yang Yue, Cheng Yuanbing. Tunneling field-effect transistor with Ge/In0.53Ga0.47As heterostructure as tunneling junction. J Appl Phys 2013, 113(9): 094502 doi: 10.1063/1.4794010
[10]
Rajoriya A, Shrivastava M. Sub 0.5 V operation of performance driven mobile systems based on area scaled tunnel FET devices. IEEE Electron Device Lett, 2013, 60(8): 2626 doi: 10.1109/TED.2013.2270566
[11]
Wu Y, Hasegawa H, Kakushima K. A novel hetero-junction tunnel-FET using semiconducting silicide-Silicon contact and its scalability. Microelectron Reliab, 2014, 54(5): 899 doi: 10.1016/j.microrel.2014.01.023
[12]
Wang Wei, Wang Pengfei, Zhang Chunmin. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans Electron Devices, 2014, 61(1): 193 doi: 10.1109/TED.2013.2289075
[13]
Kane E O. Theory of tunneling. J Appl Phys, 1961, 32(1): 83 doi: 10.1063/1.1735965
[14]
Kao K H, Verhulst A S. Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans Electron Devices, 2012, 59(2): 292 doi: 10.1109/TED.2011.2175228
[15]
Knoll L, Richter S. Strained silicon based complementary tunnel-FETs: steep slope switches for energy efficient electronics. Solid-State Electron, 2014, 98(3): 32 http://cn.bing.com/academic/profile?id=2151035196&encoded=0&v=paper_preview&mkt=zh-cn
[16]
Ford A C, Yeung C W, Chuang S. Ultrathin body InAs tunneling field-effect transistors on Si substrates. Appl Phys Lett, 2011, 98(11): 113105 doi: 10.1063/1.3567021
[17]
Kazazis D, Jannaty P, Zaslavsky A. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator. Appl Phys Lett, 2009, 94(26): 263508 doi: 10.1063/1.3168646
Fig. 1.  (Color online) Two-dimensional cross section of the simulated device structure for VDSTFET: Gate length Lg = 8 nm, source height Hs = 50 nm, drain thickness Hd = 5 nm, gate oxide thickness TOX = 2 nm, channel thickness HC = 10 nm.

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Fig. 2.  (Color online) Transfer characteristics for different values of the drain voltage for VDSTFET with abrupt doping profile. In addition,gate oxide thickness is 2 nm,Lg = 8 nm,Hs = 50，HC =5nm,Hd = 5 nm, source width Ls = 20 nm. Gate metal work function WF = 4.0 eV. The phonon-assisted BTBT model parameters have been calculated, Apath = 1.4 × 1020 cm-3s-1, Bpath = 1.12 × 108V/cm.

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Fig. 3.  (Color online) Schematic representations of (a) a linetunneling double-gate TFET and (b) a point-tunneling double-gate TFET. The arrows indicate the electrons’ band-to-band tunneling paths.

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Fig. 4.  (Color online) Electron band-to-band tunneling generation rate in the source and channel for different VGSfor VDS=1 V. (a) Line tunneling n-type TFET at VGS=0.42 V. (b) Line tunneling ntype TFET VGS=1.0 V. (c) Point tunneling n-type TFET at VGS=0.15 V. (d) Point tunneling n-type TFET VGS=0.42 V. (d) Point tunneling n-type TFET VGS=1.0 V.

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Fig. 5.  (a) Band diagram of a line-tunneling TFET perpendicular to the gate dielectric in the source region, and the shaded region marks the allowed transitions. (b) Simulated energy band diagram near the tunneling junction at a depth of 1 nm from the oxide-semiconductor interface for point tunneling TFET

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Fig. 6.  Transfer characteristics showing the impact of line tunneling and point tunneling on the threshold voltage. Simulated transfer characteristics of Si-UTFET and Si VDSTFET under the same condition. The VDSTFET shows much smaller SS and larger ION.

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Fig. 7.  (Color online) Band-to-band electron volumetric generation rate in the Si-VDSTFET. (a) Ambipolar conduction VDS=0.5 V, VGS=-0.5 V. (b) Off-state VDS=0.5 V, VGS=-0.0 V. (c) Onstate VDS=0.5 V, VGS=0.5 V.

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Fig. 8.  (Color online) The active line denotes line tunneling of electrons and holes, while the dotted line denotes point tunneling of electrons at VGS=1.0 V.

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Fig. 9.  SS of Si-VDSTFET, SiGe-UTFET and conventional planar Si-TFET as function of drain current. Drain current of above three types of TFET as function of gate voltage

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Fig. 10.  Impact of gate-length scaling on the device characteristics for Si-VDSTFET

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Fig. 11.  Impact of source thickness scaling on the device characteristics for Si-VDSTFET

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Fig. 12.  Impact of channel thickness scaling on the device characteristics for Si-VDSTFET

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Fig. 13.  (Color online) Simulated distributions of electric field and eBTBT generation rate of channel thickness is (a) 10 nm, (b) 8 nm, (c) 7 nm, (d) 5 nm at VGS = 0.2 V.

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Fig. 14.  (a) Layout of the simulated Si-VDSTFET with IDS–VGS curves for different source doing level. (b) On-state minimum tunnel width against source concentration

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Fig. 15.  Layout of the simulated Si-VDSTFET with IDS–VGS curves for different drain doping level.

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Fig. 16.  (Color online) Electron band-to-band generation rate for drain doping level (a) 1 × 1017,(b) 1 × 1018,(c) 1 × 1019,(d) 1 × 1020 cm-3. For doping = 1 × 1019 cm-3 eBTBT clearly occurs at the drain-channel junction

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Fig. 17.  (Color online) Simulated ID–VG curves for different temperatures

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[1]
Rawat G, Kumar S, Goel E, et al. Analytical modeling of subthreshold current and subthreshold swing of Gaussian doped strained-Si-on-insulator MOSFETs. Journal of Semiconductors, 2014, 35(8): 084001 doi: 10.1088/1674-4926/35/8/084001
[2]
Jiang Zhi, Zhuang Yiqi, Li Cong, et al. Drive current enhancement in TFET by dual source region. J Electric Comput Eng, 2015, 10(1): 1155 http://cn.bing.com/academic/profile?id=1602678720&encoded=0&v=paper_preview&mkt=zh-cn
[3]
Li Cong, Zhuang Yiqi, Wang Ping, et al. A new analytical model for junctionless cylindrical surrounding-gate MOSFETs. IEEE International Conference on Electron Devices and Solid-State {Circuits, 2015, 117(5) http://cn.bing.com/academic/profile?id=1999793054&encoded=0&v=paper_preview&mkt=zh-cn
[4]
Li Cong, Zhuang Yiqi, Zhang Li. A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs. Chin Phys B, 2014, 3(5): 038502 http://cn.bing.com/academic/profile?id=2250506748&encoded=0&v=paper_preview&mkt=zh-cn
[5]
Lattanzio L, De Michielis L, Ionescu A M. The electron-hole bilayer tunnel FET. Solid-State Electron, 2012, 2012(74): 85 http://cn.bing.com/academic/profile?id=2070989338&encoded=0&v=paper_preview&mkt=zh-cn
[6]
Verhulst A S, Leonelli D, Rooyackers R, et al. Drain voltage dependent analytical model of tunnel field-effect transistors. J Appl Phys, 2012, 110(2): 024510 http://cn.bing.com/academic/profile?id=2070580334&encoded=0&v=paper_preview&mkt=zh-cn
[7]
Tiwari P K, Saramekala K, Dubey S, et al. Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates. Journal of Semiconductors, 2014, 35(10): 104002 doi: 10.1088/1674-4926/35/10/104002
[8]
Richter S, Blaeser S, Trellenkamp S. SiGe on SOl nanowire array TFETs with homo- and heterostructure tunnel junctions. Ultimate Integration on Silicon (ULIS), 2013, 6523482: 25 http://cn.bing.com/academic/profile?id=2206270344&encoded=0&v=paper_preview&mkt=zh-cn
[9]
Guo Pengfei, Yang Yue, Cheng Yuanbing. Tunneling field-effect transistor with Ge/In0.53Ga0.47As heterostructure as tunneling junction. J Appl Phys 2013, 113(9): 094502 doi: 10.1063/1.4794010
[10]
Rajoriya A, Shrivastava M. Sub 0.5 V operation of performance driven mobile systems based on area scaled tunnel FET devices. IEEE Electron Device Lett, 2013, 60(8): 2626 doi: 10.1109/TED.2013.2270566
[11]
Wu Y, Hasegawa H, Kakushima K. A novel hetero-junction tunnel-FET using semiconducting silicide-Silicon contact and its scalability. Microelectron Reliab, 2014, 54(5): 899 doi: 10.1016/j.microrel.2014.01.023
[12]
Wang Wei, Wang Pengfei, Zhang Chunmin. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans Electron Devices, 2014, 61(1): 193 doi: 10.1109/TED.2013.2289075
[13]
Kane E O. Theory of tunneling. J Appl Phys, 1961, 32(1): 83 doi: 10.1063/1.1735965
[14]
Kao K H, Verhulst A S. Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans Electron Devices, 2012, 59(2): 292 doi: 10.1109/TED.2011.2175228
[15]
Knoll L, Richter S. Strained silicon based complementary tunnel-FETs: steep slope switches for energy efficient electronics. Solid-State Electron, 2014, 98(3): 32 http://cn.bing.com/academic/profile?id=2151035196&encoded=0&v=paper_preview&mkt=zh-cn
[16]
Ford A C, Yeung C W, Chuang S. Ultrathin body InAs tunneling field-effect transistors on Si substrates. Appl Phys Lett, 2011, 98(11): 113105 doi: 10.1063/1.3567021
[17]
Kazazis D, Jannaty P, Zaslavsky A. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator. Appl Phys Lett, 2009, 94(26): 263508 doi: 10.1063/1.3168646

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    Received: 25 February 2016 Revised: 06 April 2016 Online: Published: 01 September 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(9): 094003
      Zhi Jiang, Yiqi Zhuang, Cong Li, Ping Wang, Yuqi Liu. Vertical-dual-source tunnel FETs with steeper subthreshold swing[J]. Journal of Semiconductors, 2016, 37(9): 094003. doi: 10.1088/1674-4926/37/9/094003 ****Z Jiang, Y Q Zhuang, C Li, P Wang, Y Q Liu. Vertical-dual-source tunnel FETs with steeper subthreshold swing[J]. J. Semicond., 2016, 37(9): 094003. doi: 10.1088/1674-4926/37/9/094003.
      Citation:
      Zhi Jiang, Yiqi Zhuang, Cong Li, Ping Wang, Yuqi Liu. Vertical-dual-source tunnel FETs with steeper subthreshold swing[J]. Journal of Semiconductors, 2016, 37(9): 094003. doi: 10.1088/1674-4926/37/9/094003 ****
      Z Jiang, Y Q Zhuang, C Li, P Wang, Y Q Liu. Vertical-dual-source tunnel FETs with steeper subthreshold swing[J]. J. Semicond., 2016, 37(9): 094003. doi: 10.1088/1674-4926/37/9/094003.
      shu

      Vertical-dual-source tunnel FETs with steeper subthreshold swing

      DOI: 10.1088/1674-4926/37/9/094003

      • School of Microelectronic, Xidian University, Xi'an 710071, China

      Funds:

      National Natural Science Foundation of China 61204092

      Project supported by the National Natural Science Foundation of China (Nos. 61204092, 61574109).

      National Natural Science Foundation of China 61574109

      More Information
      • Corresponding author: Jiang Zhi,zjiang@xidian.edu.cn
      • Received Date: 2016-02-25
      • Revised Date: 2016-04-06
      • Published Date: 2016-09-01

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