1. Introduction

A clock is a key module in a digital circuit system. The quartz crystal oscillator, which is the conventional clock source, is regarded as the best clock generator because of outstanding performance. With the rapid development of CMOS process technology, however, the quartz crystal oscillator features some limitations, such as high power consumption, large area, and unsuitable for system on chip (SoC). Therefore, it is hard for the quartz crystal oscillator to meet the trend of CMOS process.

Nowadays, researchers have paid more attention to the on-chip clock generator^[1-7]. The low-power clock generator is divided into two classes: analog and digital. The analog clock has higher precision, as well as a larger area and higher power consumption. The band-gap voltage reference is usually adopted in the analog clock generator as voltage regulator^{[8, 9]}. However, it is difficult to design in low supply voltage because of the structure of band-gap voltage reference, and the structure also limits the decrease of supply voltage conversely. LC architecture DCO^{[10, 11]} has high accuracy with a large area of capacitance and inductance. DCO with current-starved structure^{[12, 13]} features good performance, but also needs a static current source, which leads to more static power consumption. What is more, the analog process is not suitable for process technology scaling down, which also limits the development of the analog clock generator. Compared with the analog clock, the all-digital on-chip clock generator has a higher compatibility. Though the precision is not as good as the analog clock generator, it can meet the low voltage and low-power consumption requirements.

The simplest digital clock generator is the ring oscillator with odd reversed delay cells. There are two precision limitations of digital controlled oscillator (DCO). On one hand, the delay of reversed delay cells will change with variations of process, voltage and temperature (PVT). On the other hand, the structure of DCO leads to the precision and range limitations of the output frequency. An all-digital on-chip oscillator with relative reference modeling is proposed^[14], which can eliminate the effect of PVT variations with off-chip calibration.

This paper proposes a novel hybrid DCO architecture used in the all-digital clock generator, which is based on relative reference modeling. The calibration DCO control code is designed to improve the accuracy of output frequency, as well as widen the adjustment range. High accuracy implies little error between the object frequency and the DCO output. Section 2 introduces the relative reference modeling briefly, and presents the architecture of hybrid DCO. Section 3 explains the methods of DCO code calibration. Section 4 shows the layout and simulation results, as well as makes the preference comparison between traditional and novel hybrid DCO. Finally, Section 5 summarizes this work.

2. Architecture

The clock generator based on relative reference modeling can tolerate the variations of PVT to a certain extent. The basic theory of the PVT-tolerant clock generator is illustrated at Fig. 1. For the specific ring oscillator pairs, their period features a fit curve with the variation of supply voltage and temperature. The delay ratio of the specific ring oscillator pairs can be calculated when simulated. The specific ring oscillator pairs are also designed on chip, and the delay ratio of which can be acquired by counting the pulse number in a certain time. Thus, the period of the one ring oscillator (called the cells composed of standard delay cells) under current PVT can be estimated by a look-up table algorithm, and the delay of a standard delay cell is also acquired. The DCO is also composed of standard delay cells. The DCO control code is acquired according to the object frequency and the delay of one standard delay cell. The DCO control code controls the DCO to generate a high accuracy clock. By this method, the clock generator can eliminate the effect of PVT variations.

Two aspects affect the accuracy of PVT tolerance clock generator. One is the fitting quality of ring oscillator pairs, which is decided by the number and kind of the inverse cells. The other is the precision of DCO. Once the ring oscillator pairs are determined, the precision of DCO decides the accuracy of the clock generator. Thus, a high-precision DCO is essential.

2.1 Traditional cascade DCO

To decrease the chip area, the DCO in Ref. [14] adopts the cascade architecture shown in Fig. 2. DCO is composed of ten similar groups with different number of standard delay cells. In other words, different group combination realizes different delay. Different numbers of standard delay cells are connected into DCO by MUX. Thus, the output period of DCO can be expressed as

$T_{\rm DCO} =\text{DCO_code}\times T_{\rm SDC},$

(1)

where DCO_code is the 10 bit DCO control code, and $T_{\rm \mathrm{SDC}}$ is the period of standard delay cells.

2.2 Novel hybrid DCO

The traditional DCO is simple and convenient. However, the output period of cascade DCO consists of not only the period of standard delay cells, but also the delay of MUX, which is used to select a different number of standard delay cells. What is more, wires and vias in DCO layout also introduce parasitic resistance and capacitance, which cause the extra-delay in circuit. The extra-delay caused by selectors and parasitic is named inherent delay. Thus, with the same DCO control code, the actual periods of DCO are

${T_{{\rm{DCO\_ACT}}}} = {T_{{\rm{INH}}}} + {T_{{\rm{DCO}}}} = {T_{{\rm{INH}}}} + {\rm{DCO\_code}} \times {T_{{\rm{SDC}}}},$

(2)

where $T_{\rm \mathrm{INH}}$ is the inherent delay of circuit, existing

$T_{\rm INH} =T_{\rm PARA} +T_{\rm SEL} =T_{\rm PARA} +10 T_{\rm MUX},$

(3)

where $T_{\rm \mathrm{PARA}}$ is the extra-delay caused by parasitic in layout, $T_{\rm \mathrm{SEL}}$ is the extra-delay introduced by selectors, and $T_{\rm \mathrm{MUX}}$ is the delay of one MUX. According to the theory of relative reference modeling, the DCO control code should be changed as the period of standard delay cells varies, so that the output frequency may keep stable as PVT changed. In other words, for a specified object output frequency, $T_{\rm \mathrm{DCO}}$ should be insensitive to the variations of supply voltage and temperature. However, there is

$R=\frac{T_{\rm INH} }{T_{{\rm{DCO\_ACT}}} }=\frac{T_{\rm INH} }{T_{\rm INH} +T_{\rm DCO} },$

(4)

where $R$ is the ratio of $T_{\rm \mathrm{INH}}$ and $T_{{\rm{DCO\_ACT}}}$, represent the incidence of inherent delay. The DCO control code should be modified to ensure the $T_{\rm \mathrm{DCO}}$ is stable and adjustable. $T_{\rm \mathrm{INH}}$ always exists, and is sensitive to voltage and temperature. With the increment of object output frequency, $T_{\rm \mathrm{DCO}}$ decreased, thus $R$ rise and $T_{\rm \mathrm{INH}}$ accounts for a large portion of $T_{{\rm{DCO\_ACT}}}$, which leads to worse accuracy of DCO. For the clock generator without reference clock source, the DCO output variation caused by $T_{\rm \mathrm{INH}}$ cannot be eliminated. Thus, the accuracy and the available range of DCO are badly restricted by the inherent delay.

To improve the precision of DCO, inherent delay should be as small as possible. There are two methods to reduce the inherent delay. Firstly, layout should be optimized, such as shortening the wires between the logic cells, and avoiding the signal wire across gate circuits. Secondly, DCO architecture should be improved, such as decreasing the delay introduced by selectors. Generally, layout optimization is limited, while the architecture improvement is critical.

A novel DCO with hybrid architecture is proposed in this paper. Fig. 3 presents the system architecture of the improved DCO. The DCO is divided into two parts: DCO_high and DCO_low. DCO_high and DCO_low are placed end-to-end, composing the ring oscillator together. The control code is DCOH_code and DCOL_code, respectively, controlling the delay of DCO_high and DCO_low. A code calibrating unit also exists in the system to adjust the DCO control code, so that a high accuracy clock can be acquired.

The architecture of the hybrid DCO is shown in Fig. 4. A wide range of output frequency should be involved to meet different system requirements, then the DCO contains enormous numbers of inverse cells. With DCO control code plus one, the circuit delay adds 100 ps. To balance chip area, circuit complexity, inherent delay and wire load, a six cascade stage DCO_high and a chain DCO_low with fifteen cells comprise the hybrid DCO. DCO_high decides the coarse output frequency of DCO, and adopts a cascade delaying stage with different number of cells to decrease the area and the complexity of layout. The delay of the latter stage is approximately twice the delay of the former stage, so that the DCO_high can be controlled directly by DCOH_code without decoder. The standard delay cells which form the DCO adopt NAND cells, so that the NAND connected with C[4)-C[9) can be merged with delay stages. DCO_low decides the fine output frequency of DCO, which adopts the chain structure with three-state buffer as selectors. Fifteen standard delay cells comprise the chain structure, and each odd number of standard delay cells is connected with three-state buffer. Outputs of buffer are connected together, with the input of DCO_high and the output of DCO_low. Thus, no matter whether one or fifteen standard delay cells is selected, there is only one three-state buffer connected into DCO, besides, the expected number of standard delay cells is calculated in relative reference modeling. Then

$T_{\rm INH} =T_{\rm PARA} +6 T_{\rm MUX} +T_{\rm BUF},$

(5)

where $T_{\rm \mathrm{BUF}}$ is the delay of a three-state buffer, which is much smaller than the delay of MUX. Thus, the inherent delay introduced by selectors is decreased, and the accuracy of DCO is improved. Eight dummy devices are also designed in the improved DCO to match the load. There must be one OE selected in DCO_low. In other words, when one OE is equal to one, other OEs must be zero; otherwise the circuit logic may be confused. The DCO_low also guarantees that there is an odd number of standard delay cells connected into DCO.

3. Code calibration unit

To achieve the object output frequency, the number of cells selected in DCO should be less than the DCO control code calculated by relative reference modeling because of the inherent delay. What is more, with the on-off of the logic gates in DCO_low, the coupling capacitance changed. In other words, the inherent delay of DCO may be changed because of capacitance variation selecting different OE in DCO_low. It can be calibrated in the code calibration unit.

Fig. 5 presents the calculation step in the code calibration unit. Firstly, the 10 bit original DCO control code (DCO_code_ori) can be calculated according to the object output frequency and the relative reference modeling. Secondly, the original DCO control code is split, and the number of standard delay cells corresponding to the inherent delay is acquired, being

$\text{NUM}=\frac{T_{\rm INH} }{T_{\rm CELL} },$

(6)

where $T_{\rm \mathrm{CELL}}$ is the delay of a standard delay cell. Because of the variation of coupling capacitance, different DCOL_code correspond to different NUM. Then, the original DCO control code minus NUM eliminates the effect caused by the inherent delay. The result should be adjusted into an odd number to ensure the operation of DCO. Hence, a 10 bit new DCO control code (DCO_code_new) is acquired. Next, the new DCO control code transfers into 6 bit DCOH_code (binary) and 8 bit DCOL_code (one-hot code). Adopting one-hot code can guarantee there is only one OE selected, preventing the logic from confusion. At last, both codes are sent to DCO_high and DCO_low to acquire the object frequency output.

4. Simulation and comparison

The novel hybrid DCO is composed of NAND2XL and designed in smic180 nm CMOS process. There is 6 bit control code in DCO_high and 8 bit control code in DCO_low. The output frequency of DCO is 15-120 MHz, and the frequency error is 0.83% at 25 MHz with 0-80 ℃ temperature, 1.6-2.0 V voltage variation at TT, FF, SS corner.

Fig. 6 shows the layout of the novel DCO. The chip area is 0.021 mm$^{\mathrm{2}}$. DCO_low locates in the center and DCO_high is designed around DCO_low. The blank position is filled with decoupled capacitors to reduce noise.

The simulation performance of traditional cascade DCO and the novel hybrid DCO at 25, 80, and 120 MHz in TT, FF, SS corners is shown in Fig. 7, with 1.6 to 1.8 V supply voltage variation as well as 0 to 80 ℃ temperature range. Figs. 7(a), 7(c), 7(e) show the output frequency error of hybrid DCO at 25, 80, and 120 MHz, respectively. The maximum output frequency error is 0.83%, 2.2%, and 4.8% at 25, 80, and 120 MHz, respectively. Figs. 7(b), 7(d), 7(f) show the RMS output frequency error of traditional cascade DCO and the novel hybrid DCO at 25, 80, and 120 MHz. The RMS error of hybrid DCO is smaller than that of traditional DCO in most cases. The advantage of hybrid DCO is more obvious at higher object frequency. This is because the inherent delay accounts for a large portion of the period of DCO at higher object frequency, so that the hybrid DCO with less inherent delay ensures better accuracy performance.

Monte Carlo simulation can reflect the performance of the hybrid and traditional DCO more directly. 1000 Monte Carlo simulation samples simulated results were shown in Fig. 8. The RMS Frequency Error of hybrid DCO and traditional DCO are concentrated in 1% to 1.3% and 1.2% to 1.5%, respectively. The accuracy advantage of the hybrid DCO is obvious.

Jitter describes the signal purity in the time domain. It is the characteristic of an oscillator, and reflects the short-term frequency stability. The eye diagram of the hybrid DCO was presented in Fig. 9. The simulation RMS jitter is 143.05 ps at 25 MHz.

Table 1 lists the performance comparison of recent work. Compared with other clock generators, this proposed DCO can tolerate a wider range of supply voltage and temperature, and has a smaller area as well as higher accuracy. The hybrid DCO has a wider output frequency range, so that the clock generator can meet different conditions needed, especially in the system with a higher clock need. Thus, the clock generator based on the hybrid DCO can supply a high stability, high accuracy, and voltage-and temperature-tolerant clock source to the system.

5. Conclusion

In this paper, a novel DCO with hybrid architecture is proposed. This DCO is composed of DCO_high with cascade architecture and DCO_low with chain structure. Through structure improvement and the assistance of code calibration unit, the novel DCO decreases the effect of supply voltage, temperature, as well as the inherent delay caused by DCO structure and parasitic resistance and capacitance. Compared with traditional cascade DCO architecture and other work, the novel DCO has a higher accuracy and wider available range of output frequency. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm$^{\mathrm{2}}$ chip area. The output frequency is adjusted from 15-120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6-1.8 V supply voltage and 0-80 ℃ temperature variations in TT, FF, SS corner. The jitter is 143.05 ps at 25 MHz.