J. Semicond. > 2020, Volume 41 > Issue 11 > 111402
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CMOS analog and mixed-signal phase-locked loops: An overview

Zhao Zhang1, 2,

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 Corresponding author: Zhao Zhang, Email: zhangzhao11@semi.ac.cn

DOI: 10.1088/1674-4926/41/11/111402

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Abstract: CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

Key words: phase-locked loop (PLL), charge-pump based PLL (CPPLL), ultra-low-jitter PLL, injection-locked PLL (ILPLL), sub-sampling PLL (SSPLL), sampling PLL (SPLL)



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Fig. 1.  (a). Block diagram of the basic CPPLL. (b) Transfer curve of PFD and CP. (c) Timing diagram.

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Fig. 2.  Linear phase noise model, CPPLL loop dynamics, and noise transfer functions of each building blocks.

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Fig. 3.  (Color online) (a) Timing diagram of the CPPLL with CP current mismatch. (b) VC-ripple-induced reference spur on the PLL output spectrum. (c) VC-ripple-induced deterministic jitter (DJ) on the PLL output clock eye.

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Fig. 4.  (Color online) Quantization noise effect with (a) narrow and (b) wide loop bandwidth, respectively.

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Fig. 5.  (Color online) Degradation of the in-band phase noise and fractional spur due to the PFD/CP nonlinearity.

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Fig. 6.  Schematics of CPs with current mismatch suppression techniques.

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Fig. 7.  Conceptual block diagram of the CPPLL with CP current mismatch calibration technique.

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Fig. 8.  Examples of (a) SC-LPF[33] and (b) SC-LPF with RC-LPF (sampling loop filter)[3].

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Fig. 9.  (Color online) Conceptual block diagram of (a) fully differential CPPLL and (b) CPPLL with spur frequency boosting technique.

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Fig. 10.  (Color online) Area reduction techniques: (a) capacitance multiplier, (b) dual-path loop CPPLL, (c) hybrid digital PLL, and (d) time-based PLL.

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Fig. 11.  (a) Divider with retiming DFF. (b) Divider with retiming DFF and calibration circuit for preventing metastability issue.

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Fig. 12.  (Color online) (a) Gated CP. (b) Gated CP with current mismatch suppression technique. (c) Retiming DFF operates at prescaler output frequency. (d) PLL with current reuse technique.

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Fig. 13.  AFC techniques: (a) Vtune monitoring technique, (b) relative period comparison technique, (c) counter-based AFC, (d) VCO-counting AFC, (e) four-phase counting AFC, and (f) TDC-assisted AFC.

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Fig. 14.  Fast fine locking techniques: (a) dynamic loop bandwidth switching technique, (b) frequency presetting technique, and (c) dynamic phase error compensation (DPEC) technique.

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Fig. 15.  (Color online) CP linearization techniques: (a) basic idea, (b) CP offset current technique, (c) CP offset current technique with sampling loop filter, and (d) PFD offset delay technique.

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Fig. 16.  Quantization noise suppression techniques: (a) sub-integer-N divider technique, (b) phase-interpolator (PI) based compensation technique, (c) DTC-based compensation technique, (d) phase-domain quantization noise filtering technique, (e) reference frequency multiplication technique, (f) current-mode DAC based compensation technique, (g) finite-impulse-response-embedded (FIR-embedded) noise filtering technique, and (h) space-time averaging technique.

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Fig. 17.  (Color online) ILPLL: (a) Block diagram of the basic ILPLL and the principle of the phase noise suppression of the ILPLL, (b) schematic of DILO and SILO with their injection timing, (c) ILPLL with injection timing calibration, and (d) conceptual block diagram of the ILPLL with adaptive injection timing alignment techniques.

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Fig. 18.  (Color online) SSPLL: (a) block diagram of the integer-N SSPLL, (b) timing diagram and the transfer characteristics of the SSPD/SSCP, (c) simplified block diagram of the fractional-N SSPLL, and (d) simplified block diagram of the digital SSPLL.

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Fig. 19.  SPLL: simplified block diagram of (a) the integer-N SPLL and (b) fractional-N SPLL.

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Table 1.   Summary of the features of the AMS-PLL architectures

Architecture Pros Cons Suitable application scenarios
CPPLL Simple and robust 1. CP-induced in-band phase noise is multiplied by N2 (N is division ratio)
2. Divider noise contributes in-band phase noise		 1. Jitter and PLL power requirements are not stringent
2. Generates low-jitter clock without ultra-low jitter reference clock
ILPLL Both in-band and outband phase noise are suppressed simultaneously Large spur induced at large division ratio N Generates ultra-low-jitter clock with small N and ultra-low-jitter reference clock
SSPLL 1. Ultra-low in-band phase noise
2. No divider-induced phase noise		 Narrow PD monotonic input range Generates high frequency (e. g. > 20 GHz) ultra-low-jitter clock with large N and ultra-low-jitter reference clock
SPLL 1. Ultra-low in-band phase noise
2. Wider PD monotonic input range than that of SSPLL		 Divider-induced phase noise still exists Generates low frequency (e. g. < 10 GHz) ultra-low-jitter clock with large N and ultra-low-jitter reference clock
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    Received: 02 July 2020 Revised: 20 September 2020 Online: Accepted Manuscript: 30 September 2020Uncorrected proof: 10 October 2020Published: 03 November 2020

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      Article Navigation >  Journal of Semiconductors  > 2020  >  41(11): 111402
      Zhao Zhang. CMOS analog and mixed-signal phase-locked loops: An overview[J]. Journal of Semiconductors, 2020, 41(11): 111402. doi: 10.1088/1674-4926/41/11/111402 ****Z Zhang, CMOS analog and mixed-signal phase-locked loops: An overview[J]. J. Semicond., 2020, 41(11): 111402. doi: 10.1088/1674-4926/41/11/111402.
      Citation:
      Zhao Zhang. CMOS analog and mixed-signal phase-locked loops: An overview[J]. Journal of Semiconductors, 2020, 41(11): 111402. doi: 10.1088/1674-4926/41/11/111402 ****
      Z Zhang, CMOS analog and mixed-signal phase-locked loops: An overview[J]. J. Semicond., 2020, 41(11): 111402. doi: 10.1088/1674-4926/41/11/111402.
      shu

      CMOS analog and mixed-signal phase-locked loops: An overview

      DOI: 10.1088/1674-4926/41/11/111402
      • 1.

        State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

      • 2.

        Graduate School of Advanced Science and Engineering, Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima, 739-8530, Japan

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      • Corresponding author: Email: zhangzhao11@semi.ac.cn
      • Received Date: 2020-07-02
      • Revised Date: 2020-09-20
      • Published Date: 2020-11-10

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