
PAPERS
Abstract: Eight node capacitance models are presented to generate the model library.It is proved that these models can be used to extract the capacitances from almost all of the VLSI interconnect structures.The formula for each model is also given.The numerical results show that our method is accurate.For the results obtained by formulas,it is also very fast.
Key words: model library approach, multilayer, VLSI interconnect, capacitance extraction
1 |
A crystal graph multilayer descriptor Dahai Wei Journal of Semiconductors, 2020, 41(8): 080202. doi: 10.1088/1674-4926/41/8/080202 |
2 |
Raheela Rasool, Najeeb-ud-Din, G. M. Rather Journal of Semiconductors, 2019, 40(12): 122401. doi: 10.1088/1674-4926/40/12/122401 |
3 |
Zhan Gao, Dan Ren, Shuai Yan, Xiaoyu Xu, Zhuoxiang Ren, et al. Journal of Semiconductors, 2016, 37(8): 085003. doi: 10.1088/1674-4926/37/8/085003 |
4 |
Dan Ren, Xiaoyu Xu, Hui Qu, Zhuoxiang Ren Journal of Semiconductors, 2015, 36(4): 045008. doi: 10.1088/1674-4926/36/4/045008 |
5 |
Binbin Jie, Chihtang Sah Journal of Semiconductors, 2014, 35(2): 021001. doi: 10.1088/1674-4926/35/2/021001 |
6 |
MOS Capacitance–Voltage Characteristics: IV. Trapping Capacitance from 3-Charge-State Impurities Jie Binbin, Sah Chihtang Journal of Semiconductors, 2012, 33(1): 011001. doi: 10.1088/1674-4926/33/1/011001 |
7 |
MOS Capacitance-Voltage Characteristics: V. Methods to Enhance the Trapping Capacitance Jie Binbin, Sah Chihtang Journal of Semiconductors, 2012, 33(2): 021001. doi: 10.1088/1674-4926/33/2/021001 |
8 |
Jie Binbin, Sah Chihtang Journal of Semiconductors, 2011, 32(12): 121001. doi: 10.1088/1674-4926/32/12/121001 |
9 |
MOS Capacitance–Voltage Characteristics from Electron-Trapping at Dopant Donor Impurity Jie Binbin, Sah Chihtang Journal of Semiconductors, 2011, 32(4): 041001. doi: 10.1088/1674-4926/32/4/041001 |
10 |
MOS Capacitance-Voltage Characteristics III. Trapping Capacitance from 2-Charge-State Impurities Jie Binbin, Sah Chihtang Journal of Semiconductors, 2011, 32(12): 121002. doi: 10.1088/1674-4926/32/12/121002 |
11 |
MOS structure fabrication by thermal oxidation of multilayer metal thin films Mohammad Orvatinia, Atefeh Chahkoutahi Journal of Semiconductors, 2011, 32(3): 036001. doi: 10.1088/1674-4926/32/3/036001 |
12 |
Amit Chaudhry, J. N. Roy Journal of Semiconductors, 2010, 31(11): 114001. doi: 10.1088/1674-4926/31/11/114001 |
13 |
Fu Jun Journal of Semiconductors, 2009, 30(8): 084005. doi: 10.1088/1674-4926/30/8/084005 |
14 |
Capacitance–voltage characterization of fully silicided gated MOS capacitor Wang Baomin, Ru Guoping, Jiang Yulong, Qu Xinping, Li Bingzong, et al. Journal of Semiconductors, 2009, 30(3): 034002. doi: 10.1088/1674-4926/30/3/034002 |
15 |
A Simulation of the Capacitance-Voltage Characteristics of a Ge/Si Quantum-Well Structure Cheng Peihong, Huang Shihua Journal of Semiconductors, 2008, 29(1): 110-115. |
16 |
Parameter Extraction for 2-π Equivalent Circuit Modelof RF CMOS Spiral Inductors Gao Wei, Yu Zhiping Chinese Journal of Semiconductors , 2006, 27(4): 667-673. |
17 |
Zhang Wei, Zhu Lian, Sun Qingqing, Lu Hongliang, Ding Shijin, et al. Chinese Journal of Semiconductors , 2006, 27(3): 429-433. |
18 |
Elmore Delay Estimation of Two Adjacent Coupling Interconnects Dong Gang, Yang Yintang, Li Yuejin Chinese Journal of Semiconductors , 2006, 27(1): 54-58. |
19 |
Wang Xiaofeng, Zeng Yiping, Wang Baoqiang, Zhu Zhanping, Du Xiaoqing, et al. Chinese Journal of Semiconductors , 2005, 26(9): 1692-1698. |
20 |
A New Clustering-Based Partitioning Method for VLSI Mixed-Mode Placement Lü Yongqiang, Hong Xianlong, Yang Changqi, Zhou Qiang, and Cai Yici, et al. Chinese Journal of Semiconductors , 2005, 26(1): 22-28. |
Article views: 3711 Times PDF downloads: 2049 Times Cited by: 0 Times
Received: 18 August 2015 Revised: 29 June 2007 Online: Published: 01 November 2007
Citation: |
Zhao Peng, Zhang Jie, Chen Kangsheng, Wang Haogang. A New Model Library Approach to Extract VLSI Interconnect Capacitance[J]. Journal of Semiconductors, 2007, 28(11): 1794-1802.
****
Zhao P, Zhang J, Chen K S, Wang H G. A New Model Library Approach to Extract VLSI Interconnect Capacitance[J]. Chin. J. Semicond., 2007, 28(11): 1794.
|
Journal of Semiconductors © 2017 All Rights Reserved 京ICP备05085259号-2