20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

Wang Gui , Wang Zhigong , Wang Huan , Ding Jingfeng and and Xiong Mingzhen

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Key words: demultiplexer, latch, CMOS, high-speed circuit

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Received: 19 August 2015 Revised: Online: Published: 01 October 2005

Article Navigation > Journal of Semiconductors > 2005 > 26(10): 1881-1885

Wang Gui, Wang Zhigong, Wang Huan, Ding Jingfeng, and Xiong Mingzhen. 20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS[J]. 半导体学报(英文版), 2005, 26(10): 1881-1885.

Citation:

Wang Gui, Wang Zhigong, Wang Huan, Ding Jingfeng, and Xiong Mingzhen. 20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS[J]. 半导体学报(英文版), 2005, 26(10): 1881-1885.

Wang Gui, Wang Zhigong, Wang Huan, Ding Jingfeng, and Xiong Mingzhen. 20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS[J]. 半导体学报(英文版), 2005, 26(10): 1881-1885.

Citation:

Wang Gui, Wang Zhigong, Wang Huan, Ding Jingfeng, and Xiong Mingzhen. 20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS[J]. 半导体学报(英文版), 2005, 26(10): 1881-1885.

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