Abstract: This paper introduces a novel verification development platform for the passive UHF RFID tag,which is compatible with the ISO/IEC 18000-6B standard, operating in the 915MHz ISM band.This platform efficiently reduces the design and development time and cost,and implements a fast prototype design of the passive UHF RFID tag.It includes the RFID analog front end and the tag control logic,which is implemented in an Altera ACEX FPGA.The RFID analog front end,which is fabricated using a Chartered 0.35μm two-poly four-metal CMOS process,contains a local oscillator,power on reset circuit,matching network and backscatter,rectifier,regulator,AM demodulator,etc.The platform achieves rapid,flexible and efficient verification and development,and can also be fit for other RFID standards after changing the tag control logic in FPGA.

Key words: verification development platform, passive UHF RFID, tag, FPGA