Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA

Gao , Haixia，Yang , Yintang，and , Dong and Gang

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Key words: FPGA, LUT, computation models, area, delay

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Received: 19 August 2015 Revised: Online: Published: 01 May 2005

Article Navigation > Journal of Semiconductors > 2005 > 26(5): 893-898

Gao, Haixia，Yang, Yintang，and, Dong, Gang. Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA[J]. 半导体学报(英文版), 2005, 26(5): 893-898.

Citation:

Gao, Haixia，Yang, Yintang，and, Dong, Gang. Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA[J]. 半导体学报(英文版), 2005, 26(5): 893-898.

Gao, Haixia，Yang, Yintang，and, Dong, Gang. Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA[J]. 半导体学报(英文版), 2005, 26(5): 893-898.

Citation:

Gao, Haixia，Yang, Yintang，and, Dong, Gang. Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA[J]. 半导体学报(英文版), 2005, 26(5): 893-898.

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