An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems

Zhao Bing , Qiu Yulin , Lü Tieliang and and Hei Yong

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Key words: asynchronous circuits, Viterbi decoder, ACS, response time

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Received: 19 August 2015 Revised: Online: Published: 01 May 2005

Article Navigation > Journal of Semiconductors > 2005 > 26(5): 886-892

Zhao Bing, Qiu Yulin, Lü Tieliang, and Hei Yong. An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems[J]. 半导体学报(英文版), 2005, 26(5): 886-892.

Citation:

Zhao Bing, Qiu Yulin, Lü Tieliang, and Hei Yong. An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems[J]. 半导体学报(英文版), 2005, 26(5): 886-892.

Zhao Bing, Qiu Yulin, Lü Tieliang, and Hei Yong. An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems[J]. 半导体学报(英文版), 2005, 26(5): 886-892.

Citation:

Zhao Bing, Qiu Yulin, Lü Tieliang, and Hei Yong. An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems[J]. 半导体学报(英文版), 2005, 26(5): 886-892.

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