Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies

Ting Lei; Zhehong Liu; Zhiwen Liu; Guangjie Xue; Chun Sun; Jun Zhou; Xiangshui Miao

doi:10.1088/1674-4926/25070024

J. Semicond. > Just Accepted

ARTICLES

Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies

Ting Lei^{1, 2}, Zhehong Liu², Zhiwen Liu², Guangjie Xue², Chun Sun², Jun Zhou^2, and Xiangshui Miao^1,

+ Author Affiliations

Corresponding author: Jun Zhou, Jerry_Zhou@xmcwh.com; Xiangshui Miao, miaoxs@hust.edu.cn

DOI: 10.1088/1674-4926/25070024CSTR: 10.1088/1674-4926/25070024

Abstract: The introduction of high-k/metal gate (HK/MG) technology enables independent tuning of N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) threshold voltages, facilitating advanced nodes and improving overall chip performance. However, severe pattern loading effects during PMOS device fabrication pose challenges in Dummy Poly removal. This work reports the optimization of the Photoresist Etch Back (PREB) process, providing a wider process window for subsequent AL CMP. By tuning the PR coating uniformity to 1.6% and applying four-zone Electrostatic Chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO₂ were reduced to 6.3%, 2.3%, and 5.1%, respectively. An optimized over etch (OE) recipe with a high selectivity of PR : SiN : SiO₂ ≈ 1 : 1 : 6 effectively balanced gate height loading between N- and PMOS regions. Furthermore, precise EB1 time tuning enabled defect removal, while advanced KLA inspection ensured early detection of critical failure modes. Collectively, these measures establish a robust and stable PREB process for advanced logic device fabrication.

Key words: PREB, dummy poly remove, horn height, pattern loading effect

References

[1]	Shao Q, Chen F, Jiang L, et al. High K metal gate CMP process development for 32 nm and beyond gate last approach. ECS Trans, 2013, 52(1), 523 doi: 10.1149/05201.0523ecst
[2]	Nunomura S, Morita Y. SiO₂/Si interface defects in HKMG stack fabrication. Surf Interfaces, 2025, 56, 105445 doi: 10.1016/j.surfin.2024.105445
[3]	Li Z Y, Wang X J, Jiang Y L. Metal boundary effect mitigation by HKMG thermal process optimization in FinFET integration technology. IEEE Trans Electron Devices, 2024, 71(4), 2335 doi: 10.1109/TED.2024.3370119
[4]	Choi K M. 32 nm high K metal gate (HKMG) designs for low power applications. IEEE International SoC Design Conference, 2008, I
[5]	Trentzsch M, Flachowsky S, Richter R, et al. A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs. IEEE International Electron Devices Meeting, 2016, 1
[6]	Li C Y, Wang J J, Wang S H, et al. A review of IoT applications in healthcare. Neurocomputing, 2024, 565, 127017 doi: 10.1016/j.neucom.2023.127017
[7]	Alwahedi F, Aldhaheri A, Ferrag M A, et al. Machine learning techniques for IoT security: Current research and future vision with generative AI and large language models. Internet Things Cyber Phys Syst, 2024, 4, 167 doi: 10.1016/j.iotcps.2023.12.003
[8]	Ng D T K, Lee M, Tan R J Y, et al. A review of AI teaching and learning from 2000 to 2020. Educ Inf Technol, 2023, 28(7), 8445 doi: 10.1007/s10639-022-11491-w
[9]	Yu X F, Ai T T, Wang K. Application of nanogenerators in acoustics based on artificial intelligence and machine learning. APL Mater, 2024, 12(2), 020602 doi: 10.1063/5.0195399
[10]	Chih-Lin I, Han S F, Xu Z K, et al. 5G: Rethink mobile communications for 2020+. Philos Trans A Math Phys Eng Sci, 2016, 374(2062), 20140432
[11]	Chávez-Santiago R, Szydełko M, Kliks A, et al. 5G: The convergence of wireless communications. Wirel Pers Commun, 2015, 83(3), 1617 doi: 10.1007/s11277-015-2467-2
[12]	de Azevedo A M, Lopes T J, Cardoso D D, et al. SiGe semiconductor electronic component: a review on fundamentals and applications. Obs De La Econ Latinoam, 2024, 22(12), e8370
[13]	Beyer C, Bhattacharjee N, Mikolajick T, et al. Back‐bias Effects in a SiGe Nanosheet Transistor with Multiple Independent Gates. Adv Mater Technol, 2025, 10(6), 2401391 doi: 10.1002/admt.202401391
[14]	Ji S L, Han Q H, Zhang H Y. Dummy Poly Gate Removal Scheme at FinFET. ECS Trans, 2017, 75(33), 15 doi: 10.1149/07533.0015ecst
[15]	Zeng Y Z, Zhao J, Gao H J, et al. Dummy poly removal impact factors and improvement in HKMG last process. ECS Trans, 2014, 60(1), 709 doi: 10.1149/06001.0709ecst
[16]	Huang S, Qu X F, Sun L, et al. N/P split boundary profile improvement in high K metal gate dummy poly remove process. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[17]	Li J J, Pan H M, Yu M F, et al. An optimized monitoring method for 28 HK ILD CMP. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[18]	Diao J, Leung G, Qian J, et al. ILD0 CMP: Technology enabler for high K metal gate in high performance logic devices. 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2010, 247
[19]	Ma X, Wang K L, Yu J W, et al. Study on 28NM technology node ILD0-CMP Micro_Scratch defect reduction. 2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, 1
[20]	Que Y R, Ma X, Zhang J, et al. Study on the mechanism of SIN residue for ILD0 CMP. 2023 China Semiconductor Technology International Conference (CSTIC), 2023, 1
[21]	Li Y J, Zhang B C, Yang J G, et al. Study and optimization of photo resistor etch back loop in HK metal gate. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[22]	Wang M, Chen H, Wang K, et al. The Type and Solution of Inline Poly Residue Defect for 28 HK Process Improvement. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[23]	Song Y, Yang Z H, Tang X, et al. Study of PREB process in FDSOI. 2020 China Semiconductor Technology International Conference (CSTIC), 2020, 1

Fig. 1. (Color online) Schematic of PREB Process Flow: (a) Photo exposure, (b) EB1 step, (c) EB2 ME step, (d) EB2 OE and Asher process.

DownLoad: Full-Size Img PowerPoint

Fig. 2. TEM images showing (a) "Horn Height" defect profile due to poor etch selectivity, and (b) "Little Hill" profile with over-etched SiN.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) SEM images of PR after coating: (a) Dense Narrow Poly area, (b) Large Poly area; (c) PR thickness uniformity before and after adjustment measured by ellipsometry.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) (a) EB1 PR Etch Amount and (b) Post-EB1 PR Remain versus wafer radius

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) The uniformity and range of (a) PR, (b) SiN, and (c) OX at 40/40/40/40°C; The uniformity and range of (d) PR, (e) SiN, and (f) OX at 42/40/45/48°C;

DownLoad: Full-Size Img PowerPoint

Fig. 6. TEM images after EB2 OE: (a)−(c) show excessive etch; (d)−(f) show optimized process with appropriate SiN remain.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) (a) Defect Map highlighting HM_OX residue; (b) KLA inspection image of HM_OX defect; (c) TEM cross-section of HM_OX residue; (d) Summary table of EB1/EB2 split experiments.

DownLoad: Full-Size Img PowerPoint

[1]	Shao Q, Chen F, Jiang L, et al. High K metal gate CMP process development for 32 nm and beyond gate last approach. ECS Trans, 2013, 52(1), 523 doi: 10.1149/05201.0523ecst
[2]	Nunomura S, Morita Y. SiO₂/Si interface defects in HKMG stack fabrication. Surf Interfaces, 2025, 56, 105445 doi: 10.1016/j.surfin.2024.105445
[3]	Li Z Y, Wang X J, Jiang Y L. Metal boundary effect mitigation by HKMG thermal process optimization in FinFET integration technology. IEEE Trans Electron Devices, 2024, 71(4), 2335 doi: 10.1109/TED.2024.3370119
[4]	Choi K M. 32 nm high K metal gate (HKMG) designs for low power applications. IEEE International SoC Design Conference, 2008, I
[5]	Trentzsch M, Flachowsky S, Richter R, et al. A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs. IEEE International Electron Devices Meeting, 2016, 1
[6]	Li C Y, Wang J J, Wang S H, et al. A review of IoT applications in healthcare. Neurocomputing, 2024, 565, 127017 doi: 10.1016/j.neucom.2023.127017
[7]	Alwahedi F, Aldhaheri A, Ferrag M A, et al. Machine learning techniques for IoT security: Current research and future vision with generative AI and large language models. Internet Things Cyber Phys Syst, 2024, 4, 167 doi: 10.1016/j.iotcps.2023.12.003
[8]	Ng D T K, Lee M, Tan R J Y, et al. A review of AI teaching and learning from 2000 to 2020. Educ Inf Technol, 2023, 28(7), 8445 doi: 10.1007/s10639-022-11491-w
[9]	Yu X F, Ai T T, Wang K. Application of nanogenerators in acoustics based on artificial intelligence and machine learning. APL Mater, 2024, 12(2), 020602 doi: 10.1063/5.0195399
[10]	Chih-Lin I, Han S F, Xu Z K, et al. 5G: Rethink mobile communications for 2020+. Philos Trans A Math Phys Eng Sci, 2016, 374(2062), 20140432
[11]	Chávez-Santiago R, Szydełko M, Kliks A, et al. 5G: The convergence of wireless communications. Wirel Pers Commun, 2015, 83(3), 1617 doi: 10.1007/s11277-015-2467-2
[12]	de Azevedo A M, Lopes T J, Cardoso D D, et al. SiGe semiconductor electronic component: a review on fundamentals and applications. Obs De La Econ Latinoam, 2024, 22(12), e8370
[13]	Beyer C, Bhattacharjee N, Mikolajick T, et al. Back‐bias Effects in a SiGe Nanosheet Transistor with Multiple Independent Gates. Adv Mater Technol, 2025, 10(6), 2401391 doi: 10.1002/admt.202401391
[14]	Ji S L, Han Q H, Zhang H Y. Dummy Poly Gate Removal Scheme at FinFET. ECS Trans, 2017, 75(33), 15 doi: 10.1149/07533.0015ecst
[15]	Zeng Y Z, Zhao J, Gao H J, et al. Dummy poly removal impact factors and improvement in HKMG last process. ECS Trans, 2014, 60(1), 709 doi: 10.1149/06001.0709ecst
[16]	Huang S, Qu X F, Sun L, et al. N/P split boundary profile improvement in high K metal gate dummy poly remove process. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[17]	Li J J, Pan H M, Yu M F, et al. An optimized monitoring method for 28 HK ILD CMP. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[18]	Diao J, Leung G, Qian J, et al. ILD0 CMP: Technology enabler for high K metal gate in high performance logic devices. 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2010, 247
[19]	Ma X, Wang K L, Yu J W, et al. Study on 28NM technology node ILD0-CMP Micro_Scratch defect reduction. 2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024, 1
[20]	Que Y R, Ma X, Zhang J, et al. Study on the mechanism of SIN residue for ILD0 CMP. 2023 China Semiconductor Technology International Conference (CSTIC), 2023, 1
[21]	Li Y J, Zhang B C, Yang J G, et al. Study and optimization of photo resistor etch back loop in HK metal gate. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[22]	Wang M, Chen H, Wang K, et al. The Type and Solution of Inline Poly Residue Defect for 28 HK Process Improvement. 2022 China Semiconductor Technology International Conference (CSTIC), 2022, 1
[23]	Song Y, Yang Z H, Tang X, et al. Study of PREB process in FDSOI. 2020 China Semiconductor Technology International Conference (CSTIC), 2020, 1

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Received: 16 July 2025 Revised: 18 September 2025 Online: Accepted Manuscript: 23 October 2025

Article Navigation > Journal of Semiconductors > 2025 > Accepted Manuscript

Ting Lei, Zhehong Liu, Zhiwen Liu, Guangjie Xue, Chun Sun, Jun Zhou, Xiangshui Miao. Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25070024 ****T Lei, Z H Liu, Z W Liu, G J Xue, C Sun, J Zhou, and X S Miao, Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25070024

Citation:

T Lei, Z H Liu, Z W Liu, G J Xue, C Sun, J Zhou, and X S Miao, Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25070024

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Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies

DOI: 10.1088/1674-4926/25070024

CSTR: 10.1088/1674-4926/25070024

1.
College of Integrated Circuits, Huazhong University of Science and Technology, WuHan, 430000, China
2.
Wuhan Xinxin Semiconductor Manufacturing Corporation, WuHan, 430000, China

More Information

Ting Lei graduated with a Ph.D. from the University of Science and Technology of China (USTC) in 2023. He is currently a Senior Process Integration Engineer at Wuhan XinXin Semiconductor Manufacturing Co., Ltd., focusing on the research and development of advanced logic chips
Jun Zhou got his bachelor’s degree in 2004 from Wuhan University of Technology and his master’s degree in 2014 from Wuhan University. He is currently the head of research and development. In Wuhan XinXin Semiconductor Manufacturing Co., Ltd. His research focuses on advanced logic and non-volatile memory technology research
Xiangshui Miao graduated from Huazhong University of Science and Technology (HUST) in 1996. He is currently the Dean of the School of Integrated Circuits at HUST. His research focuses on information storage materials and devices, including 3D phase-change memory, memristors, and brain-inspired computing and logic operations
Corresponding author: Jerry_Zhou@xmcwh.com; miaoxs@hust.edu.cn
Received Date: 2025-07-16
Revised Date: 2025-09-18

Available Online: 2025-10-23

Abstract

Abstract

The introduction of high-k/metal gate (HK/MG) technology enables independent tuning of N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) threshold voltages, facilitating advanced nodes and improving overall chip performance. However, severe pattern loading effects during PMOS device fabrication pose challenges in Dummy Poly removal. This work reports the optimization of the Photoresist Etch Back (PREB) process, providing a wider process window for subsequent AL CMP. By tuning the PR coating uniformity to 1.6% and applying four-zone Electrostatic Chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO₂ were reduced to 6.3%, 2.3%, and 5.1%, respectively. An optimized over etch (OE) recipe with a high selectivity of PR : SiN : SiO₂ ≈ 1 : 1 : 6 effectively balanced gate height loading between N- and PMOS regions. Furthermore, precise EB1 time tuning enabled defect removal, while advanced KLA inspection ensured early detection of critical failure modes. Collectively, these measures establish a robust and stable PREB process for advanced logic device fabrication.
- PREB,
- dummy poly remove,
- horn height,
- pattern loading effect

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References(23)