Fig. 1.
(Color online) Next-generation edge AI chips with computing-centric CIM and memory-centric INMC.
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Journal of Semiconductors
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2026
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| Citation: |
Xin Si, Xing Wang, Jun Yang. Computing-centric computing-in-memory and memory-centric in-/near-memory computing for DNNs and transformer based LLMs[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26040029
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X Si, X Wang, and J Yang, Computing-centric computing-in-memory and memory-centric in-/near-memory computing for DNNs and transformer based LLMs[J]. J. Semicond., 2026, 47(7): 070202 doi: 10.1088/1674-4926/26040029
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Computing-centric computing-in-memory and memory-centric in-/near-memory computing for DNNs and transformer based LLMs
DOI: 10.1088/1674-4926/26040029
CSTR: 32376.14.1674-4926.26040029
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References
[1] Wang X, Du Y C, Jiao T H, et al. A 28nm 127.54TFLOPS/W MXFP6 and 117.42 TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 512-513[2] Agarwal A, Hsu S K, Anders M A, et al. A 147 TOPS/W, 250 TOPS/mm2, Fully Synthesizable, Digital Compute-in-Memory Accelerator Supporting INT8×INT8 with Zero-Point Quantization in Intel 18A Technology. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 528-529[3] Cao Y, Jiang J H, Jiang H J, et al. A 1.2GHz 12.77 GB/s/mm2 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 524-525[4] Dong P C, Tan Y H, Liu X J, et al. A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 532-533[5] Shen J Z, Zhou Z D, Zha W F, et al. A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 514-515[6] Hsu H H, Khwa W S, Yeh Y K, et al. A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026, 516-517[7] Tien J C, Khwa W S, Hsieh L J, et al. A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 520-521[8] Li W Z, Wang B H, Zhou Z D, et al. A 16Mb 166.8TOPS/W Near-Memory Phase-Domain-Computing Ferroelectric NAND Flash for Approximate Nearest Neighbor Search on Edge Devices. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 522-523[9] Yeh Y K, Su J W, Hsu T H, et al. A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-In-Memory Macro for Hybrid SNN-CNN Edge Computing. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 526-527[10] Feng L C, Liu Y L, Wu L, et al. A 28nm 106.85TOPS/W and 77.68TFLOPS/W CIM Macro with Stage-Wise-Enabled Lossless Compressors Based on Sign-Bit-Embedded Transition-Counting-Lines for Edge-AI Devices. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 518-519[11] You D Q, Khwa W S, Zhang B, et al. A 22nm 104.5TOPS/W μ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks. 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025: 250-251[12] Wang X, Jiao T H, Yang Y, et al. A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two’s-Complement MAC for CNNs and Transformers, 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025, 254-255[13] Chen X, Li S C, Zhang Z C, et al. A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025: 260-261 -
Proportional views



Xin Si received the B.S. and Ph.D. degrees in integrated circuit design and integration system from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2016 and 2020, respectively. Since 2021, he has been an Associate Professor with the School of Integrated Circuits, Southeast University (SEU), Nanjing, China. He has an extensive publication record, including over 30 conference papers/journal articles, notably 17 ISSCC papers and 11 JSSC articles. His current research interests encompass memory, computing-in-memory circuits, and AI chip designs. Dr. Si serves as an International Technical Program Committee Member for IEEE MCSoC and VLSI-DAT.
Xing Wang received his B.S. degree in electronic science and engineering from Southeast University, Nanjing, China, in 2023. He is currently pursuing the Ph.D. degree of integrated circuit engineering in Southeast University, Nanjing, China. His current research interests include floating-point computing in memory and AI accelerator.
Jun Yang received the B.S. and Ph.D. degrees in electronic engineering from Southeast University, Nanjing, China, in 1999 and 2004, respectively. He is currently a Professor with the National ASIC System Engineering Research Center, Southeast University. He has authored and co-authored over 50 technical articles in conferences and journals, including ISSCC, DAC, JSSC and TVLSI. He has authorized over 100 Chinese and U.S. invention patents. His current researches focus on SRAM design, inmemory computing, and near-threshold design. Dr. Yang serves as an International Technical Program Committee Member for ISSCC and ASSCC.
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