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A photolithography-compatible method for transferring full-device constituents on silicon substrate

Zunxian Lv1, Shun Zhang1, Mingjian Yang1, Xinsheng Wang1, Zhaochao Liu1, Yameng Hou1, 2, Jiabiao Chen1, , Moyuan Cao1, Feng Luo1 and Jinxiong Wu1,

+ Author Affiliations

 Corresponding author: Jiabiao Chen, jbchen@nankai.edu.cn; Jinxiong Wu, jxwu@nankai.edu.cn

DOI: 10.1088/1674-4926/26080030CSTR: 32376.14.1674-4926.26080030

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Abstract: Transfer printing offers a promising route to integrate pre-fabricated device components with two-dimensional (2D) semiconductors, yet most existing approaches rely on deliberately deposited buffer layers or specialized substrates, adding complexity and limiting compatibility with standard silicon fabrication. Here, we report a simple and photolithography-compatible strategy that leverages the ultrathin lift-off-resist (LOR) residue, which naturally retains on a commercial silicon substrate after standard photolithography, as a sacrificial release layer. This ~2 nm-thick residue allows selective water intercalation at the LOR/Si interface, enabling damage-free delamination of various pre-fabricated metal electrodes, high-κ metal gate (HKMG) stacks, and even entire device stacks directly from the Si substrate. Besides, the top-gated MoS2 transistor was fabricated by one-step laminating the full-device stack onto the MoS2 flake, yielding a clean van der Waals interface, small subthreshold swing and negligible gate hysteresis. Our method eliminates the need for additional sacrificial layer deposition or specialized handling substrates, offering a facile method to transfer full-device constituents on industry-compatible Si substrate.

Keywords: transfer printing, photolithography, LOR residue, full-device stacks, commercial silicon substrate



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Fig. 1.  (Color online) Basic properties of the lift-off-resist (LOR) residue layer on a Si substrate after bilayer resist photolithography process. (a) Schematic illustration of the photolithography process using the well-known bilayer photoresist (LOR + S1813) on Si substrate, demonstrating a thin layer of LOR residual remaining on the Si substrate after UV exposure and the development process. (b) Typical optical microscope (OM) image of the Si substrate after photolithography, in which the LOR residual layer is almost unnoticeable. (c) Typical atomic force microscopy (AFM) images of the UV-exposed Si substrate with different development time ranging from 50 s to 5 min. (d) The extracted surface roughness (Ra) of Si substrate as a function of development duration. (e) Contact angle images of water droplets on a heavily doped p-type silicon (p++) Si substrate before (upper) and after photolithography (bottom). (f) N 1s spectra of X-ray photoelectron spectroscopy (XPS) of the LOR residual layer on Si substrate in reference to the bare Si substrate and the spin-coated LOR resist. (g) PL spectroscopy for the LOR residual layers on a Si substrate in reference to the bare Si substrate and the spin-coated LOR resist.

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Fig. 2.  (Color online) Transfer of metal electrodes on Si substrate assisted by LOR residual layer. (a) Schematic illustration of transferring metal electrodes patterned by the S1813/LOR bilayer resist process onto a Si substrate. Typically, an adhesive polymer layer of polystyrene (PS) film is spin-coated onto the metal patterns, followed by peeling off in water assisted by a polydimethylsiloxane (PDMS) stamp. (b) Cross-sectional bright-field TEM image of the Au/p++ Si interface after LOR-containing lithography patterning, showing a clear LOR residual layer between the Au and the Si substrate. (c) High-resolution TEM image of the corresponding Au/Si interface, indicating that the ultrathin LOR residual layer is ~1.8 nm thick. (d) Typical photograph of the PDMS/PS/Au/Si stack, which is immersed in water for the peeling-off process. (e) Photograph of the Au pattern transferred onto the PS/PDMS supporter. (f) Typical OM images of transferred Ag, Pd, Pt, Cr, Ti, and Ni metals on the PS/PDMS supporter. Here, the Ag, Pd, and Pt represent the weak adhesive metals to Si, and Cr, Ti, and Ni represent those with strong adhesion. (g)−(h) Typical AFM images for the bottom side of transferred Au (g) and Ti (h), showing a clean and smooth surface after peeling off from the Si substrate. (i) AFM height histograms of metal surfaces transferred onto the PS supporter.

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Fig. 3.  (Color online) Transfer of high-κ metal gate (HKMG) patterns on Si substrate. (a) Schematic illustration of the process flow for fabricating and transferring HKMG patterns on Si substrate. (b) and (c) Typical photograph (b) and corresponding OM image (c) of as-patterned HKMG (Al2O3/Cr/Ag) on Si substrate. (d) and (e) Typical photograph (d) and corresponding OM image (e) of the HKMG transferred onto the PS/PDMS supporter. (f) Cross-sectional high-angle annular dark-field (HAADF) image of the as-patterned HKMG on Si and corresponding EDS mapping images for the Si, C, Al, Cr, Ag, and mix elements, indicating the presence of LOR residual layer between the Si substrate and Al2O3.

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Fig. 4.  (Color online) One-step transfer of entire device stack and van der Waals integration with MoS2. (a) Schematic of the one-step transfer and integrated process to fabricate fully encapsulated top-gated transistors. Typically, the source/drain contacts are In/Ag (5/30 nm) prepared by thermal evaporation, and the dielectric is 13 nm Al2O3 grown by atomic layer deposition (ALD). (b)−(f) Typical photograph and OM images of FET arrays fabricated on Si substrate (b), (e), capped with spin-coated PS films (c), (f) and peeled off to the PDMS supporter (d). (g) Typical AFM image of the backside of field-effect transistor (FET) arrays transferred onto PDMS, showing a surface roughness of 0.36 nm for the Al2O3. (h) Typical OM image of a top-gated MoS2 FET fabricated on SiO2/Si substrate by one-step transfer. (i) Cross-sectional HAADF and corresponding EDS mapping images for the Si, S, C, and Al elements. The clear C element signal at the interface between the MoS2 and Al2O3 suggests that the LOR residual layer was transferred off from Si substrate and stacked on top of MoS2 surface.

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Fig. 5.  (Color online) MoS2 top-gate transistor fabricated via the one-step transfer and integration process. (a) Schematic illustration of the fabricated top-gate MoS2 transistor, whose contact and top-gate metals are In/Ag (5/30 nm) and Cr/Ag (8/45 nm), respectively. The MoS2 channel has a thickness of ~5 nm, and the thickness of Al2O3 was 13 nm. (b) Typical dual-sweep transfer curves of the MoS2 FET measured under different Vds from 0.05 to 0.5 V. (c) Corresponding output curves measured under different gate voltages (Vg) ranging from 1 to −2 V with a Vg step of −0.5 V. (d) and (e) Dual-sweep transfer curves of the MoS2 FET with different Vg sweeping ranges (d) and sweeping rates (e). (f) and (g) Extracted gate hysteresis as a function of the bias range (f) and the sweep rate (g).

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    Received: 27 August 2026 Revised: 22 September 2026 Online: Accepted Manuscript: 12 October 2026

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      Article Navigation >  Journal of Semiconductors  > 2026  > Accepted Manuscript
      Zunxian Lv, Shun Zhang, Mingjian Yang, Xinsheng Wang, Zhaochao Liu, Yameng Hou, Jiabiao Chen, Moyuan Cao, Feng Luo, Jinxiong Wu. A photolithography-compatible method for transferring full-device constituents on silicon substrate[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26080030 ****Z Lv, S Zhang, M J Yang, X S Wang, Z C Liu, Y M Hou, J B Chen, M Y Cao, F Luo, and J X Wu, A photolithography-compatible method for transferring full-device constituents on silicon substrate[J]. J. Semicond., 2026, 47(10): 102709 doi: 10.1088/1674-4926/26080030
      Citation:
      Zunxian Lv, Shun Zhang, Mingjian Yang, Xinsheng Wang, Zhaochao Liu, Yameng Hou, Jiabiao Chen, Moyuan Cao, Feng Luo, Jinxiong Wu. A photolithography-compatible method for transferring full-device constituents on silicon substrate[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26080030 ****
      Z Lv, S Zhang, M J Yang, X S Wang, Z C Liu, Y M Hou, J B Chen, M Y Cao, F Luo, and J X Wu, A photolithography-compatible method for transferring full-device constituents on silicon substrate[J]. J. Semicond., 2026, 47(10): 102709 doi: 10.1088/1674-4926/26080030
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      A photolithography-compatible method for transferring full-device constituents on silicon substrate

      DOI: 10.1088/1674-4926/26080030
      CSTR: 32376.14.1674-4926.26080030
      • 1.

        Tianjin Key Lab for Rare Earth Materials and Applications, Collaborative Innovation Center of Materials Science, School of Materials Science and Engineering, Academy for Advanced Interdisciplinary Studies, Nankai University, Tianjin, 300350, China

      • 2.

        Key Laboratory of Advanced Energy Materials Chemistry, Ministry of Education, College of Chemistry, Nankai University, Tianjin 300350,China

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      • Zunxian Lv is a PhD candidate at the School of Materials Science and Engineering, Nankai University. He is currently conducting her research under the supervision of Prof. Jinxiong Wu at Nankai University. His research focuses on transfer and integration of 2D Materials
      • Jiabiao Chen got his B.S. degree in 2021 and Ph.D. degree in 2026 at Nankai University. Now he is a postdoctoral researcher at Nankai University under the supervision of Prof. Jinxiong Wu. His research interests include the development of 2D gate-dielectric materials and high-performance nanoelectronics
      • Jinxiong Wu has been a Professor at the School of Materials Science and Engineering, Nankai University, since 2019. He obtained his Ph.D. degree in Physical Chemistry from Peking University at 2017, then continued his postdoctoral program in the same University during 2017~2019. His research focuses on high-mobility and high-κ 2D materials based functional devices
      • Corresponding author: jbchen@nankai.edu.cn; jxwu@nankai.edu.cn
      • Received Date: 2026-08-27
      • Revised Date: 2026-09-22
        • Available Online: 2026-10-12

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