Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Shi Weihua; Hong Zhiliang; Hu Chaohong; Kang Yong

doi:10.1088/1674-4926/30/8/085012

J. Semicond. > 2009, Volume 30 > Issue 8 > 085012

SEMICONDUCTOR INTEGRATED CIRCUITS

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Shi Weihua, Hong Zhiliang, Hu Chaohong and Kang Yong

+ Author Affiliations

DOI: 10.1088/1674-4926/30/8/085012

Abstract: This paper presents an implementation for improving muti-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. The CHE I_g temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase I_g according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

Key words: temperature self-adaptive programming; 65 nm multi-level cell flash memory; program throughput

1	Substrate temperature dependent studies on properties of chemical spray pyrolysis deposited CdS thin films for solar cell applications Kiran Diwate, Amit Pawbake, Sachin Rondiya, Rupali Kulkarni, Ravi Waykar, et al. Journal of Semiconductors, 2017, 38(2): 023001. doi: 10.1088/1674-4926/38/2/023001
2	A simple chemical route to synthesize the umangite phase of copper selenide (Cu₃Se₂) thin film at room temperature Balasaheb M. Palve, Sandesh R. Jadkar, Habib M. Pathan Journal of Semiconductors, 2017, 38(6): 063003. doi: 10.1088/1674-4926/38/6/063003
3	6T SRAM cell analysis for DRV and read stability Ruchi, S.Dasgupta Journal of Semiconductors, 2017, 38(2): 025001. doi: 10.1088/1674-4926/38/2/025001
4	Large area perovskite solar cell module Longhua Cai, Lusheng Liang, Jifeng Wu, Bin Ding, Lili Gao, et al. Journal of Semiconductors, 2017, 38(1): 014006. doi: 10.1088/1674-4926/38/1/014006
5	Memristive SRAM cell of seven transistors and one memristor Patrick W. C. Ho, Haider Abbas F. Almurib, T. Nandha Kumar Journal of Semiconductors, 2016, 37(10): 104002. doi: 10.1088/1674-4926/37/10/104002
6	Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs Mini Bhartia, Arun Kumar Chatterjee Journal of Semiconductors, 2015, 36(4): 044003. doi: 10.1088/1674-4926/36/4/044003
7	Electro-magnetic weak coupling optical polaron and temperature effect in quantum dot M. Tiotsop, A. J. Fotue, S. C. Kenfack, N. Issofa, A. V. Wirngo, et al. Journal of Semiconductors, 2015, 36(10): 102001. doi: 10.1088/1674-4926/36/10/102001
8	The storage lifetime model based on multi-performance degradation parameters Haochun Qi, Xiaoling Zhang, Xuesong Xie, Changzhi Lü Journal of Semiconductors, 2014, 35(10): 104012. doi: 10.1088/1674-4926/35/10/104012
9	Structural parameters improvement of an integrated HBT in a cascode configuration opto-electronic mixer Hassan Kaatuzian, Hadi Dehghan Nayeri, Masoud Ataei, Ashkan Zandi Journal of Semiconductors, 2013, 34(9): 094001. doi: 10.1088/1674-4926/34/9/094001
10	Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications R. K. Singh, Neeraj Kr. Shukla, Manisha Pattanaik Journal of Semiconductors, 2012, 33(5): 055001. doi: 10.1088/1674-4926/33/5/055001
11	A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process Bai Na, Lü Baitao Journal of Semiconductors, 2012, 33(6): 065008. doi: 10.1088/1674-4926/33/6/065008
12	Design and implementation of a programming circuit in radiation-hardened FPGA Wu Lihua, Han Xiaowei, Zhao Yan, Liu Zhongli, Yu Fang, et al. Journal of Semiconductors, 2011, 32(8): 085012. doi: 10.1088/1674-4926/32/8/085012
13	Local charge neutrality condition, Fermi level and majority carrier density of a semiconductor with multiple localized multi-level intrinsic/impurity defects Ken K. Chin Journal of Semiconductors, 2011, 32(11): 112001. doi: 10.1088/1674-4926/32/11/112001
14	Design and implementation of adaptive slope compensation in current mode DC–DC onverter Guo Zhongjie, Wu Longsheng, Liu Youbao Journal of Semiconductors, 2010, 31(12): 125004. doi: 10.1088/1674-4926/31/12/125004
15	Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance Dong Yaoqi, Kong Weiran, Nhan Do, Wang Shiuh-Luen, Lee Gabriel, et al. Journal of Semiconductors, 2010, 31(6): 064012. doi: 10.1088/1674-4926/31/6/064012
16	Temperature: a critical parameter affecting the optical properties of porous silicon Long Yongfu, Ge Jin, Ding Xunmin, Hou Xiaoyuan Journal of Semiconductors, 2009, 30(6): 063002. doi: 10.1088/1674-4926/30/6/063002
17	Extraction of Temperature Parameters and Optimization of the Mextram 504 Model on SiGe HBT Ren Zheng, Hu Shaojian, Jiang Bin, Wang Yong, Zhao Yuhang, et al. Journal of Semiconductors, 2008, 29(5): 960-964.
18	Parameter Extraction for 2-π Equivalent Circuit Modelof RF CMOS Spiral Inductors Gao Wei, Yu Zhiping Chinese Journal of Semiconductors , 2006, 27(4): 667-673.
19	Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling Deng Ning, Pan Liyang, Liu Zhihong, Zhu Jun, Chen Peiyi, et al. Chinese Journal of Semiconductors , 2006, 27(3): 454-458.
20	A Low Power SRAM/SOI Memory Cell Design Yu Yang, Zhao Qian, Shao Zhibiao Chinese Journal of Semiconductors , 2006, 27(2): 318-322.

Search

GET CITATION

Shi Weihua, Hong Zhiliang, Hu Chaohong, Kang Yong. Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory[J]. Journal of Semiconductors, 2009, 30(8): 085012. doi: 10.1088/1674-4926/30/8/085012

Shi W H, Hong Z L, Hu C H, Kang Y. Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory[J]. J. Semicond., 2009, 30(8): 085012. doi: 10.1088/1674-4926/30/8/085012.

Export: BibTex EndNote

Article Metrics

Article views: 4269 Times PDF downloads: 1180 Times Cited by: 0 Times

History

Received: 18 August 2015 Revised: 27 March 2009 Online: Published: 01 August 2009

This paper presents an implementation for improving muti-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. The CHE I_g temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase I_g according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

DOI: 10.1088/1674-4926/30/8/085012

Abstract

References

Proportional views

Catalog

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

DOI: 10.1088/1674-4926/30/8/085012

Abstract

References

Proportional views

Catalog

Export File

Citation

Format

Content