1. Introduction

In modern wireless cellular systems including WCDMA, GSM, TD-LTE, and TD-LTE Advanced, there is a growing need for advanced digital-to-analog converters (DACs) with low power and high dynamic performance. For the reasons of being intrinsically faster and more linear, the segmented current-steering DAC is an ideal candidate.

For communication systems, two DACs are needed to convert I and Q digital modulated signals coming from the digital signal processor (DSP) into analog waveforms. These baseband signals are then shifted to radio frequency (RF) by the quadrature modulators. The performance of the modulator is limited by the mismatches between I and Q signals, such as gain, offset, and timing mismatches^[1]. However, these two signal paths may not be matched perfectly inside the same device due to process gradient, temperature variation, and mechanical stress. Traditionally, additional hardware such as DC offset and gain correction circuits are employed after the DAC to improve the analog signals^{[2, 3]}. And superior I/Q matching of a DAC can relax the necessity of these extra circuits.

This paper presents a current-steering DAC that is capable of handling data up to 120 Msample/s with 12-bit resolution. It generates two-channel quadrature signals for a wireless transmitter. A gain match circuit is proposed to enhance gain match between the I and Q channels. A current-switch cell with small glitch energy is designed to improve the dynamic performance of the DAC. The paper is organized as follows. In Section 2, the design of the DAC architecture and the features of the functional blocks are described. Section 3 presents the measurement results. Finally, in Section 4 conclusions are drawn.

2. DAC circuit design

The proposed DAC with two channels is a current steering architecture realized in a 1.2/2.5 V dual voltage. To meet the initial specifications for the linearity and glitch energy, while keeping a reasonable core size and digital complexity, the top 7 bits of this 12-bit DAC are decoded into 127 unary segments, while the remaining 5 bits drive a binary weighted array^[4].

Figure 1 shows the top level diagram of the converter. In this design, use of mixed voltage allows the analog section to be operated from higher supply voltages than the digital section and thus provide larger output voltage compliance and swing. The digital logics such as flip–flops, thermometer decoders, and latches operate under a 1.2 V supply. The analog circuits such as current reference and switch drivers and current sources are powered by a 2.5 V supply. As a result, an optimal balance between low power consumption and dynamic performance at high output frequencies is achieved.

2.1 Current reference circuit with gain adjustment

2.1.1   Full-scale output current adjustment

The proposed DAC is required to design a full-scale output current with adjust range 2 to 10 mA. To realize current adjustment, the unary current is generated from a bandgap voltage. The circuitry involved, shown in Fig. 2(a), utilizes an OTA to form a current-control loop with the help of a NMOS and an internal variable resistor.

In Fig. 2, it is shown that the resistance voltage is equal to the reference voltage according to a virtual short circuit. So the unary current $I_{\rm ref}$ is equal to $V_{\rm ref}$/$R_{\rm T}$. The variable resistor $R_{\rm T}$ is a digitally controlled resistor with a series of MOS switches that are controlled by signal S1–S7. The unary current through $R_{\rm T}$ can be adjusted in up to eight levels from 15 to 80 $\mu$A.

2.1.2   Gain matching for I/Q channel

Mismatch of I/Q DAC in wireless transmitters determines the waveform quality factor of the transmit signal as given in Eq. (1).

$\rho =\frac{C}{C+N}=\frac{1}{{\rm evm}^2+1},$

(1)

where $C$ stands for carrier power, $N$ is for noise power, and evm stands for error vector magnitude of transmit signals. In wireless transmitters, I/Q mismatch of I/Q DAC contributes to the noise power after a quadrature up-conversion and results in an increase of a residual side band (RSB) image. Gain mismatch is a very critical parameter for signal quality, for example it is required to be less than 5% for the RF transmitter.

The DAC's gain for current steering architecture can be defined as follows:

${\rm Gain\_DAC}=\frac{I_{\rm out} [2^N-1]-I_{\rm out} [0]}{2^N-1},$

(2)

where $N$ is the DAC's resolution. From Eq. (2), the output current variation could impact gain match between the I/Q channel. The saturation current of individual PMOS current source is described as follows:

$I_{\rm source} =\frac{\mu _{\rm p} C_{\rm ox} }{2} \frac{W_{\rm p}}{L_{\rm p}} \left(V_{\rm SG} -\left| {V_{\rm thp} } \right|\right)^2.$

(3)

Equation (3) shows that the mobility and threshold voltage shift of PMOS current sources in I/Q DAC directly contribute to current mismatch of the I/Q DAC and results in current errors between the I and Q channels. Pelgrom^[5] gives the random mismatch for the standard deviation of saturation current for two identically sized devices. The formulas are

$\frac{\sigma ^2(I)}{I^2}=\frac{4\sigma ^2(V_{\rm T} )}{(V_{\rm GS} -V_{\rm T})^2}+\frac{\sigma ^2(\beta )}{\beta ^2},$

(4)

$\sigma ^2(V_{\rm T})=\frac{A_{V_{\rm T}}^2 }{W L}+S_{V_{\rm T}}^2 D^2,$

(5)

$\frac{\sigma ^2(\beta )}{\beta ^2}=\frac{A_\beta ^2 }{W L}+S_\beta ^2 D^2,$

(6)

where $\beta$ $=$ $\mu_{n}C_{\rm ox}W/L$, $A_{\rm VT}$, $A_{\beta }$, $S_{\rm VT}$, $S_{\beta}$ are process constants, $W, L$ are device dimensions and $D$ is distance between devices.

In each channel DAC, the adequate device area required for random matching is calculated according to INL bound^[6] and optimized switching sequences^{[7, 8]} are adopted to reduce gradient error. Nevertheless, the current source arrays for an I/Q DAC are placed in one chip separately and the distance between the corresponding current cells in each DAC is long. Hence the output current of these two DACs still have large mismatch error according to Eq. (5, 6). In Ref. ^[9], the unit current sources for different channels are divided into many parts and mixed together in order to match the static characteristics. However, it needs complex wiring, which would bring larger parasitical capacitance. In this paper, a special gain matching circuitry is designed to reduce gain mismatch between the I and Q channels.

Statistical and process corner simulations of the variation of the full scale output current due to mismatch, process variations show a worst case variation of $\Delta$$I_{\rm FS}$ $=$ 24%$\cdot I_{\rm FS}$. In this design, we convert the mismatch of full scale current into one of unary current between these two channels; that is, the variation of the full scale output current are averaged into every unary unit. So the maximum variation for unary current is $\Delta I_{\rm MSB}=\Delta I_{\rm FS}$/128 $=$ 24%$\cdot I_{\rm MSB}$ for 7$+$5 architecture. Assuming a desired trimming accuracy $I_{\rm trim,lSB}$ is 1/16$\cdot I_{\rm LSB}$ $=$ 1/(16$\cdot$32)$\cdot I_{\rm MSB}$. The number of control bits is determined by the following expression:

${\rm Bits} \geqslant \frac{\ln \left( {\dfrac{\Delta I_{\rm MSB} }{I_{\rm trim,lSB} }+1} \right)}{\ln 2}.$

(7)

From Eq. (7), Bits $\geqslant$ 6.94. An extra bit should be needed to control adjust direction. So an 8-bit gain matching circuit is designed here.

As shown in Fig. 2(b), gain matching circuitry is composed of two fine gain control circuits. The I/Q DAC can adjust unary current independently by the external control signal IFG [7:0] and QFG [7:0]. Each gain control circuit has an array of PMOS and NMOS current mirrors with a series of switches. For I-channel, when current addition (positive adjust) is needed, IFG^[7] should be equal to 1'b1, switch SPI is ON and switch SNI is OFF. Currents from the PMOS mirrors flow into the node (a). The drain current of PI7 is equal to $I_{\rm ref}$. The flow of ${I_{{\rm{trim - p}}}}$ into node (a) adds ${I_{{\rm{trim - p}}}}$ to $I_{\rm ref}$ giving the total current across the NI7 as ${I_{{\rm{trim - p}}}}$ $+$ $I_{\rm ref}$. The current ${I_{{\rm{trim - p}}}}$ depends on the switching sequence of PMOS switches that be controlled by IFG[6:0]. Transistors PI0 to PI6 are used to mirror bandgap current to obtain different binary weighted currents (1/8I, 1/4I, 1/2I, I, 2I, 4I, 8I, suppose $I=$ 1/64$\cdot I_{\rm ref})$ through appropriate transistors width sizes (1/8$W, 1/4W, 1/2W, 1W, 2W, 4W, 8W$ respectively). On the other hand, switch SPI is OFF and switch SNI is ON when IFG^[7] $=$ 1'b0. A part of $I_{\rm ref}$ flows into node (b). The current across the NI7 is $I_{\rm ref}$ – ${I_{{\rm{trim - N}}}}$. Current $I_{\rm N,k}$ is mirrored into the NMOS current mirror with transistors sized appropriately to generate the same currents as in the PMOS network. The same applies to the Q-channel. So the unary current after adjustment can be expressed as

$I_{\rm MSB} =I_{\rm ref} +{\rm FG}[7]\cdot \sum\limits_{i=0}^6 {{\rm FG}[i]\cdot I_{\rm P,i} } -\overline {{\rm FG}[7]} \cdot \sum\limits_{j=0}^6 {{\rm FG}[i]\cdot I_{\rm N,j} } .$

(8)

Gain matching is achieved by adjusting the values of signal IFG and QFG. Starting from the default values of 8'h80, raise or decrease the value of one channel control signal a few steps until it can be determined if the current gain mismatch between the I and Q channels is decreased. If the gain mismatch increases, remove the step and try the same adjustment on the other channel. Iterate steps are continued until the mismatch cannot be improved further. The technique using the switches and current mirrors provides a bidirectional current gain adjustment to match I and Q channel.

2.2 Switched-current cell

In order to support full scale current variation from 2 to 10 mA, it is necessary to boost the output impedance of the DAC by 5 times for 10 mA output currents. The current sources use two levels of cascade to satisfy this requirement for the DAC. In Fig. 3(a), PMOS device MP1 is the main current source and MP2 and MP3 is the first and second cascade transistor respectively. So the output impedance is

$R_{\rm sw} \cong g_{\rm m4} g_{\rm m3} g_{\rm m2} r_{\rm o4} r_{\rm o3} r_{\rm o2} r_{\rm o1} .$

(9)

The design of the switch addresses charge feedthrough phenomena, spikes and the excursion of the voltage on the switch common source node. When the switch is turned off, the charge of the channel disappears and the charges in the overlap capacitances vary according to the gate voltage swing. The charge injected into the switch common source or output node is

$Q_{\rm inj} =Q_{\rm ch} +Q_{\rm ov} \\ =\alpha \left[{C_{\rm ox} WL_{\rm eff} \left( {V_{\rm GS}-V_{\rm TH} } \right)} \right] -C_{\rm ox} Wx_{\rm ov} \left( {V_{\rm H} -V_{\rm L}} \right),$

(10)

where $x_{\rm ov}$ being the extent of source and drain overlap, and $\alpha$ is the fraction of channel charge go to the source or drain.

Equation (10) shows that the inherent low swing operation is needed to reduce feed through. When turning off the device, the voltage on the gate is not needed to be any higher than that on the source ($V_{\rm gs}$ $=$ 0). This reduces any feed through. In Fig. 3(b), the PMOS device M1 is scaled to mimic one of the output switches. The gate voltage $V_{\rm on }$of M1 is the voltage for switch on. The voltage $V_{\rm off}$ will be equal to the voltage $V_{\rm on}$ plus M1's $V_{\rm gs}$, and uses this voltage for the off switch gate. Since the output of the driver connects to the multiplexer that be controlled by input data, the output impedance of the switch driver should be low in order to avoid intersymbol interference corrupting switching waveforms at high speed. In Fig. 3(b), the feedback is formed by adding transistor M2 and current mirror M3/M4. The impedance at node $V_{\rm off}$ is

$R_{\rm out} =r_{\rm o4} /\!/\frac{(r_{\rm o1} +r_{\rm o2} )+\dfrac{1}{g_{\rm m3} }/\!/r_{\rm o3} }{A}\approx r_{\rm o4} /\!/\frac{r_{\rm o1} +r_{\rm o2} }{A},$

(11)

where $A$ is current mirror's gain. This feedback can regulate the output impedance by adjusting value $A$.

In order to reduce glitch energy further, the conventional switch current cell in Fig. 3(a) has been improved by inserting four cascade switch transistors MP6–MP9. As shown in Fig. 3(c), the source and drain of the switching transistors are decoupled from the common source node and output node respectively. For a high to low transition of the signal Sw_p, the voltage variation at the output is, $\Delta V_{\rm out+}$ $=$ 0, because the transistor MP8 is cut off and the path between the output node and drain of the switching transistor is open. On the other hand, for a high to low transition, the transistor MP8 is in saturation, and the voltage fluctuation at the source of the transistor MP8 is small because it is a low impedance node. Hence, the voltage fluctuation at the source node of MP8 is given by

$\Delta V_{\rm S,MP8} =\frac{R_{\rm L} }{(g_{\rm m,MP8} +g_{\rm mb,MP8} )r_{\rm o,MP8} }C_{\rm gd,MP4} \frac{\Delta V_{\rm Sw\_p} }{t_{\rm r}},$

(12)

where $R_{\rm L}$ is load resistor of output, $C_{\rm gd}$ is the gate–drain capacitance of the switching transistor, and $t_{\rm r}$ is rise time of the switch signal. The intrinsic gain of MP8 determines the amount of charge to be absorbed. Transistors MP6/MP7 mostly operate in the saturation region during switching instants, thereby resulting in fast signal settling and reduced overshoot and ringing in the output currents.

3. Test

The DAC was fabricated using a TSMC 0.13 $\mu$m 1P8M CMOS process. The chip photograph of the DAC is shown in Fig. 4. The left and right parts are dedicated to I-channel and Q-channel, respectively. The central part is reserved for bandgap reference and the I/Q fine gain control circuit. Here symmetry is maximally respected in order to not induce systematic mismatch between I and Q channel. The chip occupies an effective area of 0.9 $\times$ 1.2 mm$^{2}$. The PCB was designed to make symmetrical measurement of chip performances for I and Q channels. Four 75 $\Omega$ external resistors were connected between the current output pin and ground.

Gain matching is the ratio of the gain of one DAC to the gain of the other DAC and it is calculated by^[10]

${\rm GainMatch}=\left| {\frac{\rm Gain\_DAC1-Gain\_DAC2}{\rm Gain\_DAC1}} \right|\times 100,$

(13)

where Gain_DAC is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Under 10 mA of full scale output current, gain matching between I-channel DAC and Q-channel DAC was firstly measured by setting IFG/QFG to be zero. The digital input codes of dual DAC were driven by the 12-bit periodical digital series of "000000000000" and "111111111111". An RF transformer was used to convert the differential output signal into a single-ended one that was connected to the signal probe and the ground probe of the digital oscilloscope, such that the differential signal of dual channel DAC was measured. The output voltage swings for I-channel and Q-channel are 1.485 V and 1.5337 respectively. According to Eq. (13), the value of GainMatch between I-channel and Q-channel DAC was 3.175%. Because the gain of I-channel DAC is smaller than ideal value (1.5 V), the signal IFG could be started from 8'h81. On the contrary, the signal QFG could be started from 8'h01. After a series of iterate steps, the signal IFG and QFG are finally set to 8'h89 and 8'h12 respectively for an optimum matching. At this time, the output voltage swings for I-channel and Q-channel are 1.501 V and 1.499 V respectively, as shown in Fig. 5. The gain match between these two channels was reduced to 0.13%.

In order to measure the maximum glitch energy, the transition of input digital codes to DAC has been made from "011111111111" to "100000000000", such that the glitch energy has been measured to be 23 pV-s as shown in Fig. 6.

The most important performance aspect for the communication applications is output spectrum of the the DAC. As an input signal of 1 MHz was applied to the DAC with a sampling frequency of 120 MHz, the DAC was able to reconstruct the original sinusoidal wave with SFDR of 75 dB and THD of $-73$ dB, as presented in Fig. 7. Figure 8 shows the SFDR as a function of the output signal frequency under different sample rates. When the signal is closer to the Nyquist rate, SFDRs are about 55–60 dB. DAC's noise performance could be characterized by noise spectral density (NSD) which is the noise power per unit of bandwidth. Figure 9 shows the NSD with respect to output signal frequency under 120 MHz sample rate. Table 1 summarizes the performance comparison of the proposed DAC with those of the 12-bit two channel DACs published previously.

4. Conclusion

In this paper, a 12-bit two channel current-steering DAC is demonstrated. It operates on two power supplies, 1.2 V for digital circuits and 2.5 V for analog circuits. An on-chip 8-bits bidirectional gain matching circuitry is used to improve matching performance between the I and Q channels. The gain match between the I-channel DAC and the Q-channel DAC is measured to be approximately 0.13% by gain adjustment. An improved switch and current cells are used to get better dynamic performance for the DAC under different output current and common voltage. Measurement shows SFDR is about 75 dBc at an output of 1 MHz sine wave when clocked at 120 MHz. The core area of the DAC is 1.08 mm$^{2}$ and the total power consumption is 62 mW under 120 MHz sample rate.