1. Introduction
In modern wireless cellular systems including WCDMA, GSM, TD-LTE, and TD-LTE Advanced, there is a growing need for advanced digital-to-analog converters (DACs) with low power and high dynamic performance. For the reasons of being intrinsically faster and more linear, the segmented current-steering DAC is an ideal candidate.
For communication systems, two DACs are needed to convert I and Q digital modulated signals coming from the digital signal processor (DSP) into analog waveforms. These baseband signals are then shifted to radio frequency (RF) by the quadrature modulators. The performance of the modulator is limited by the mismatches between I and Q signals, such as gain, offset, and timing mismatches[1]. However, these two signal paths may not be matched perfectly inside the same device due to process gradient, temperature variation, and mechanical stress. Traditionally, additional hardware such as DC offset and gain correction circuits are employed after the DAC to improve the analog signals[2, 3]. And superior I/Q matching of a DAC can relax the necessity of these extra circuits.
This paper presents a current-steering DAC that is capable of handling data up to 120 Msample/s with 12-bit resolution. It generates two-channel quadrature signals for a wireless transmitter. A gain match circuit is proposed to enhance gain match between the I and Q channels. A current-switch cell with small glitch energy is designed to improve the dynamic performance of the DAC. The paper is organized as follows. In Section 2, the design of the DAC architecture and the features of the functional blocks are described. Section 3 presents the measurement results. Finally, in Section 4 conclusions are drawn.
2. DAC circuit design
The proposed DAC with two channels is a current steering architecture realized in a 1.2/2.5 V dual voltage. To meet the initial specifications for the linearity and glitch energy, while keeping a reasonable core size and digital complexity, the top 7 bits of this 12-bit DAC are decoded into 127 unary segments, while the remaining 5 bits drive a binary weighted array[4].
Figure 1 shows the top level diagram of the converter. In this design, use of mixed voltage allows the analog section to be operated from higher supply voltages than the digital section and thus provide larger output voltage compliance and swing. The digital logics such as flip–flops, thermometer decoders, and latches operate under a 1.2 V supply. The analog circuits such as current reference and switch drivers and current sources are powered by a 2.5 V supply. As a result, an optimal balance between low power consumption and dynamic performance at high output frequencies is achieved.
2.1 Current reference circuit with gain adjustment
2.1.1 Full-scale output current adjustment
The proposed DAC is required to design a full-scale output current with adjust range 2 to 10 mA. To realize current adjustment, the unary current is generated from a bandgap voltage. The circuitry involved, shown in Fig. 2(a), utilizes an OTA to form a current-control loop with the help of a NMOS and an internal variable resistor.
In Fig. 2, it is shown that the resistance voltage is equal to the reference voltage according to a virtual short circuit. So the unary current
2.1.2 Gain matching for I/Q channel
Mismatch of I/Q DAC in wireless transmitters determines the waveform quality factor of the transmit signal as given in Eq. (1).
ρ=CC+N=1evm2+1, |
(1) |
where
The DAC's gain for current steering architecture can be defined as follows:
Gain_DAC=Iout[2N−1]−Iout[0]2N−1, |
(2) |
where
Isource=μpCox2WpLp(VSG−|Vthp|)2. |
(3) |
Equation (3) shows that the mobility and threshold voltage shift of PMOS current sources in I/Q DAC directly contribute to current mismatch of the I/Q DAC and results in current errors between the I and Q channels. Pelgrom[5] gives the random mismatch for the standard deviation of saturation current for two identically sized devices. The formulas are
σ2(I)I2=4σ2(VT)(VGS−VT)2+σ2(β)β2, |
(4) |
σ2(VT)=A2VTWL+S2VTD2, |
(5) |
σ2(β)β2=A2βWL+S2βD2, |
(6) |
where
In each channel DAC, the adequate device area required for random matching is calculated according to INL bound[6] and optimized switching sequences[7, 8] are adopted to reduce gradient error. Nevertheless, the current source arrays for an I/Q DAC are placed in one chip separately and the distance between the corresponding current cells in each DAC is long. Hence the output current of these two DACs still have large mismatch error according to Eq. (5, 6). In Ref. [9], the unit current sources for different channels are divided into many parts and mixed together in order to match the static characteristics. However, it needs complex wiring, which would bring larger parasitical capacitance. In this paper, a special gain matching circuitry is designed to reduce gain mismatch between the I and Q channels.
Statistical and process corner simulations of the variation of the full scale output current due to mismatch, process variations show a worst case variation of
Bits⩾ln(ΔIMSBItrim,lSB+1)ln2. |
(7) |
From Eq. (7), Bits
As shown in Fig. 2(b), gain matching circuitry is composed of two fine gain control circuits. The I/Q DAC can adjust unary current independently by the external control signal IFG [7:0] and QFG [7:0]. Each gain control circuit has an array of PMOS and NMOS current mirrors with a series of switches. For I-channel, when current addition (positive adjust) is needed, IFG[7] should be equal to 1'b1, switch SPI is ON and switch SNI is OFF. Currents from the PMOS mirrors flow into the node (a). The drain current of PI7 is equal to
IMSB=Iref+FG[7]⋅6∑i=0FG[i]⋅IP,i−¯FG[7]⋅6∑j=0FG[i]⋅IN,j. |
(8) |
Gain matching is achieved by adjusting the values of signal IFG and QFG. Starting from the default values of 8'h80, raise or decrease the value of one channel control signal a few steps until it can be determined if the current gain mismatch between the I and Q channels is decreased. If the gain mismatch increases, remove the step and try the same adjustment on the other channel. Iterate steps are continued until the mismatch cannot be improved further. The technique using the switches and current mirrors provides a bidirectional current gain adjustment to match I and Q channel.
2.2 Switched-current cell
In order to support full scale current variation from 2 to 10 mA, it is necessary to boost the output impedance of the DAC by 5 times for 10 mA output currents. The current sources use two levels of cascade to satisfy this requirement for the DAC. In Fig. 3(a), PMOS device MP1 is the main current source and MP2 and MP3 is the first and second cascade transistor respectively. So the output impedance is
Rsw≅gm4gm3gm2ro4ro3ro2ro1. |
(9) |
The design of the switch addresses charge feedthrough phenomena, spikes and the excursion of the voltage on the switch common source node. When the switch is turned off, the charge of the channel disappears and the charges in the overlap capacitances vary according to the gate voltage swing. The charge injected into the switch common source or output node is
Qinj=Qch+Qov=α[CoxWLeff(VGS−VTH)]−CoxWxov(VH−VL), |
(10) |
where
Equation (10) shows that the inherent low swing operation is needed to reduce feed through. When turning off the device, the voltage on the gate is not needed to be any higher than that on the source (
Rout=ro4//(ro1+ro2)+1gm3//ro3A≈ro4//ro1+ro2A, |
(11) |
where
In order to reduce glitch energy further, the conventional switch current cell in Fig. 3(a) has been improved by inserting four cascade switch transistors MP6–MP9. As shown in Fig. 3(c), the source and drain of the switching transistors are decoupled from the common source node and output node respectively. For a high to low transition of the signal Sw_p, the voltage variation at the output is,
ΔVS,MP8=RL(gm,MP8+gmb,MP8)ro,MP8Cgd,MP4ΔVSw_ptr, |
(12) |
where
3. Test
The DAC was fabricated using a TSMC 0.13
Gain matching is the ratio of the gain of one DAC to the gain of the other DAC and it is calculated by[10]
GainMatch=|Gain_DAC1−Gain_DAC2Gain_DAC1|×100, |
(13) |
where Gain_DAC is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Under 10 mA of full scale output current, gain matching between I-channel DAC and Q-channel DAC was firstly measured by setting IFG/QFG to be zero. The digital input codes of dual DAC were driven by the 12-bit periodical digital series of "000000000000" and "111111111111". An RF transformer was used to convert the differential output signal into a single-ended one that was connected to the signal probe and the ground probe of the digital oscilloscope, such that the differential signal of dual channel DAC was measured. The output voltage swings for I-channel and Q-channel are 1.485 V and 1.5337 respectively. According to Eq. (13), the value of GainMatch between I-channel and Q-channel DAC was 3.175%. Because the gain of I-channel DAC is smaller than ideal value (1.5 V), the signal IFG could be started from 8'h81. On the contrary, the signal QFG could be started from 8'h01. After a series of iterate steps, the signal IFG and QFG are finally set to 8'h89 and 8'h12 respectively for an optimum matching. At this time, the output voltage swings for I-channel and Q-channel are 1.501 V and 1.499 V respectively, as shown in Fig. 5. The gain match between these two channels was reduced to 0.13%.
In order to measure the maximum glitch energy, the transition of input digital codes to DAC has been made from "011111111111" to "100000000000", such that the glitch energy has been measured to be 23 pV-s as shown in Fig. 6.
The most important performance aspect for the communication applications is output spectrum of the the DAC. As an input signal of 1 MHz was applied to the DAC with a sampling frequency of 120 MHz, the DAC was able to reconstruct the original sinusoidal wave with SFDR of 75 dB and THD of
![]() |
4. Conclusion
In this paper, a 12-bit two channel current-steering DAC is demonstrated. It operates on two power supplies, 1.2 V for digital circuits and 2.5 V for analog circuits. An on-chip 8-bits bidirectional gain matching circuitry is used to improve matching performance between the I and Q channels. The gain match between the I-channel DAC and the Q-channel DAC is measured to be approximately 0.13% by gain adjustment. An improved switch and current cells are used to get better dynamic performance for the DAC under different output current and common voltage. Measurement shows SFDR is about 75 dBc at an output of 1 MHz sine wave when clocked at 120 MHz. The core area of the DAC is 1.08 mm