Fig. 1.
Block diagram of the proposed DAC.
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| Citation: |
Hualian Tang, Yiqi Zhuang, Xin Jing, Li Zhang. An I/Q DAC with gain matching circuit for a wireless transmitter[J]. Journal of Semiconductors, 2013, 34(6): 065006. doi: 10.1088/1674-4926/34/6/065006
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H L Tang, Y Q Zhuang, X Jing, L Zhang. An I/Q DAC with gain matching circuit for a wireless transmitter[J]. J. Semicond., 2013, 34(6): 065006. doi: 10.1088/1674-4926/34/6/065006.
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An I/Q DAC with gain matching circuit for a wireless transmitter
DOI: 10.1088/1674-4926/34/6/065006
More Information
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Abstract
This paper presents a two-channel 12-bit current-steering digital-to-analog converter (DAC) for I and Q signal paths in a wireless transmitter. The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA. A gain matching circuit is proposed to reduce gain mismatch between the I and Q channels. The tuning range is ±24% of full scale and the minimum resolution is 1/16 LSB. To further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch energy. The chip has been processed in a standard 0.13 μm CMOS technology. Gain mismatch between a I-channel DAC and a Q-channel DAC is measured to be approximately 0.13%. At 120-MSPS sample rate for 1 MHz sinusoidal signal, the spurious free dynamic range (SFDR) is 75 dB. The total power dissipation is 62 mW and has an active area of 1.08 mm2.-
Keywords:
- digital-to-analog converter,
- gain,
- mismatch,
- switch,
- current cell
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References
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