1. Introduction

In order to realize higher-speed and higher-packing density MOS integrated circuits, the dimensions of MOSFETs have continued to shrink according to the scaling law proposed by Dennard et al.^[1]. However, the power consumption of modern VLSI's has become rather significant as a result of extremely large integration. Reducing this power is strongly desired. Choosing a lower power supply voltage is an effective method. However, it leads to the degradation of MOSFET current driving capability. Consequently, scaling of MOS dimensions is important in order to improve the drivability, and to achieve higher-performance and higher-functional VLSIs.

The drivability is related to the average electron transport velocity traveling through the channel, which is related to the electric field distribution along the channel. In a field effect transistor, electrons enter into the channel with a low initial velocity, gradually accelerated toward the drain. As numerous numerical simulations of FETs indicate, the maximum electron drift velocity is reached near the drain^[2]. The electrons move very fast in the region near the drain but relatively slow in the region near the source. Hence, the speed of the device is affected by a relatively slow electron drift velocity in the channel near the source region.

In 1999, Long et al.^[3] proposed a new gate structure called the dual material gate (DMG) MOSFET. In the DMG MOSFET, the work function of metal gate 1 (M1) is greater than metal gate 2 (M2). The DMG MOSFET will induce the step potential at the interface between the different gate materials and make a peak electric field in the channel region that improves the carrier transit speed and increases the device driving capability. Owing to the screen effects of DMG MOSFET, the high electric field near the drain side can be effectively reduced, which suppresses the hot carrier effects (HCEs) and reduces the substrate current leakage. Up to now, many DMG MOSFETs have been investigated and expected to suppress the short channel effects (SCEs) and enhance the carrier transport efficiency^[4-10]. In China, there are also some people who carried out research on the DMG MOSFET and gave the accurate analytical model of DMG MOSFET^[11-15]. Polishchuk et al.^[16] proposed the fabrication of the DMG MOSFET.

Inspired by the DMG MOSFET, a new device structure called the single material double work function gate (SMDWG) MOSFET is introduced. In the SMDWG MOSFET, the gate is split into two parts. The gate near the source (S-gate) is composed of p$^+$ polysilicon, and the gate near the drain (D-gate) is composed of n$^+$ polysilicon. The S-gate and the D-gate have different work functions. In this paper, on the basis of the exact solution of 2-D Poisson equation, a new compact analytical model of potential is presented. The calculated results of the model match well with those simulated by the device simulator MEDICI. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.

2. Two-dimensional model for surface potential

A schematic structure of the SMDWG MOSFET is shown in Fig. 1 with S-gate and D-gate of lengths $L_1$ and $L_2 $, respectively. The source and drain regions are rectangular and uniformly doped with the concentration of $N_{\rm D}$. The channel doping concentration $N_{\rm A}$ is also uniform. The gate oxide thickness is $t_{\rm ox}$. The device characteristics were simulated using the 2-D device simulator MEDICI. The 2-D potential distribution $\phi (x, y)$ can be obtained by solving 2-D Poisson's equation. Assuming that the impurity density in the channel region is uniform and the influence of charge carriers and fixed oxide charge on the electrostatics of the channel can be ignored, the potential distribution in the silicon thin film, before the onset of strong inversion, can be expressed as^[17]

$ $$\begin{equation} \frac{{\rm d}^2\phi (x, y)}{{\rm d}x^2}+\frac{{\rm d}^2\phi (x, y)}{{\rm d}y^2}=\frac{qN_{\rm A}}{\varepsilon _{\rm Si} }, \quad 0\leqslant x\leqslant L_1 +L_2, \end{equation}$$ $

(1)

where $\phi (x, y)$ is the potential distribution in the channel, $N_{\rm A}$ is the substrate doping concentration, q is the electronic charge, and $\varepsilon _{\rm Si} $ is the permittivity of silicon.

The potential profile in the vertical direction, i.e., the y-dependence of $\phi (x, y)$ is assumed to be a third-order polynomial, i.e.,

$ $$\begin{equation} \phi (x, y)=\phi _{\rm S} (x)+C_1 (x)y+C_2 (x)y^2+C_3 (x)y^3, \end{equation}$$ $

(2)

where $\phi _{\rm S} (x)$ is the surface potential in channel, $C_1 (x)$, $C_2 (x)$ and $C_3 (x)$ are the arbitrary coefficients.

A channel depletion width parameter $\xi $^[18] that relates effective depletion width d for short-channel devices $W_1$ to that of a long-channel device is $d=\xi W_1$ where $\xi =\frac{1}{1-2\exp (-\frac{L_1 +L_2 }{\lambda _{\rm d} })}$, $W_1 =\sqrt {\frac{2\varepsilon _{\rm Si} (2\phi _{\rm F} +V_{\rm Sub} )}{qN_{\rm A}}} $, $\lambda _{\rm d} =0.65 (W_{\rm S} +W_{\rm D})$ with $W_{\rm S} $ and $W_{\rm D} $ corresponding to the depletion width from source-to-channel region and drain-to-channel region, respectively, and are given as $W_{\rm S} =\sqrt {\frac{2\varepsilon _{\rm Si} N_{\rm D} V_{\rm bi} }{qN_{\rm A} (N_{\rm A} +N_{\rm D} )}} $, $W_{\rm D} =\sqrt {\frac{2\varepsilon _{\rm Si} N_{\rm D} (V_{\rm bi} +V_{\rm DS} )}{qN_{\rm A} (N_{\rm A} +N_{\rm D} )}} $, $V_{\rm bi}$ is the built-in potential given by $V_{\rm bi} =\frac{kT}{q}\ln \frac{N_{\rm A} N_{\rm D} }{n_{\rm i}^2}$, where $n_i $ is the intrinsic carrier concentration of silicon, $V_{\rm DS} $ is the source to drain voltage, $\phi _{\rm F}$ is Fermi potential given by $\phi _{\rm F} =\frac{kT}{q}\ln \frac{N_{\rm A} }{n_{\rm i}}$, and $V_{\rm Sub}$ is the substrate bias.

In the SMDWG structure, since the gate is divided into two parts, the potential under the S-gate and the D-gate can be written as

$ $$\begin{equation} \begin{split} \phi _1 (x, y)= \phi _{\rm S1} (x)+C_{11} (x)y+C_{12} (x)y^2{}& +C_{13} (x)y^3, \\& 0\leqslant x\leqslant L_1, \end{split} \end{equation}$$ $

(3)

$ $$\begin{equation} \begin{split} \phi _2 (x, y)= \phi _{\rm S2} (x)+C_{21} (x)y+C_{22} {}& (x)y^2+C_{23} (x)y^3, \\& L_1 \leqslant x\leqslant L_1 +L_2, \end{split} \end{equation}$$ $

(4)

where $\phi _{\rm S1} (x)$ is the surface potential in the channel under S-gate, and $\phi _{\rm S2} (x)$ is the surface potential in the channel under D-gate.

The Poisson's equation is solved separately under the two gate regions using the following boundary conditions.

(1) Electric flux at the gate oxide/Si film interface is continuous.

$ $$\begin{equation} \frac{{\rm d}\phi _{\rm 1} (x, y)}{{\rm d}y}\Big|_{y=0} =\frac{\varepsilon _{\rm ox} }{\varepsilon _{\rm Si} }\frac{\phi _{\rm S1} (x)-V_{\rm GS1}' }{t_{\rm ox} }, \quad {\rm S-gate}, \end{equation}$$ $

(5)

$ $$\begin{equation} \frac{{\rm d}\phi _2 (x, y)}{{\rm d}y}\Big| _{y=0} =\frac{\varepsilon _{\rm ox} }{\varepsilon _{\rm Si} }\frac{\phi _{\rm S2} (x)-V_{\rm GS2}' }{t_{\rm ox} }, \quad {\rm D-gate}, \end{equation}$$ $

(6)

where $\varepsilon _{\rm ox} $ is the dielectric constant of the oxide, $V_{\rm GS1}' =V_{\rm GS} -V_{\rm FB1} $, and $V_{\rm GS2}' =V_{\rm GS} -V_{\rm FB2} $ where $V_{\rm GS}$ is the gate to source bias voltage, $V_{\rm FB1} $ and $V_{\rm FB2} $ are the flat-band voltages of S-gate and D-gate, respectively.

$ V_{\rm FB1} =\phi _{\rm M1}-\phi _{\rm S}, \quad V_{\rm FB2} =\phi _{\rm M2}-\phi _{\rm S}, $

where $\phi _{\rm M1} $, $\phi _{\rm M2}$ are the work function of S-gate and D-gate, $\phi _{\rm S}$ is the semiconductor work function given by $\phi _{\rm S} =\chi _{\rm S} +\frac{E_{\rm g} }{2q}+\phi _{\rm F}$.

(2) Electric field at the depletion edge is zero.

$ $$\begin{equation} \frac{{\rm d}\phi _1 (x, y)}{{\rm d}y}\Big| _{y=d} =\frac{{\rm d}\phi _2 (x, y)}{{\rm d}y}\Big| _{y=d} =0, \end{equation}$$ $

(7)

where d is the depletion width.

(3) At the depletion edge,

$ $$\begin{equation} \phi _{\rm 1} (x, d)=\phi _2 (x, d)=-V_{\rm Sub} . \end{equation}$$ $

(8)

The arbitrary constants $C_{11} (x)$, $C_{12} (x)$, $C_{13} (x)$, $C_{21} (x)$, $C_{22} (x)$ and $C_{23} (x)$ can be deduced using Eqs. (5)-(8), i.e.,

$ C_{11} (x)=-\frac{\varepsilon _{\rm ox} }{\varepsilon _{\rm Si} }\frac{V_{\rm GS1}'-\phi _{\rm S1} (x)}{t_{\rm ox} }, \\ C_{12} (x)=\frac{-3\phi _{\rm S1} (x)+2dC_{11} (x)}{d^2}, \\ C_{13} (x)=-\frac{dC_{11} (x)+2\phi _{\rm S1} (x)}{d^3}, \\ C_{21} (x)=-\frac{\varepsilon _{\rm ox} }{\varepsilon _{\rm Si} }\frac{V_{\rm GS2}'-\phi _{\rm S2} (x)}{t_{\rm ox} }, \\ C_{22} (x)=\frac{-3\phi _{\rm S1} (x)+2dC_{21} (x)}{d^2}, \\ C_{23} (x)=-\frac{dC_{21} (x)+2\phi _{\rm S1} (x)}{d^3}, $

substituting the above arbitrary constants in Eqs. (3) and (4), we get $\phi _1 (x, y)$ and $\phi _2 (x, y)$, i.e.,

$ $$\begin{equation} \begin{split} \phi _1 (x, y)={}& \phi _{\rm S1} (x)-\frac{\varepsilon _{\rm ox} }{\varepsilon _{\rm Si} }\frac{V_{\rm GS1}' -\phi _{\rm S1} (x)}{t_{\rm ox}}y \\& +\left\{ \frac{3+{2d\varepsilon _{\rm ox} }/{(t_{\rm ox} }\varepsilon _{\rm Si} )}{d^2} [V_{\rm GS1}'-\phi _{\rm S1} (x)]\right. \\& \left. -\frac{3(V_{\rm GS1}' +V_{\rm Sub} )}{d^2}\right\} y^2 \\& -\left\{ \frac{2+{2d\varepsilon _{\rm ox} }/ {(t_{\rm ox} \varepsilon _{\rm Si} })}{d^3}[V_{\rm GS1}'-\phi _{\rm S1} (x)]\right. \\& \left. -\frac{2(V_{\rm GS1}' +V_{\rm Sub} )}{d^3}\right\} y^3. \\ \end{split} \end{equation}$$ $

(9)

$ $$\begin{equation} \begin{split} \phi _2 (x, y)={}& \phi _{\rm S2} (x)-\frac{\varepsilon _{\rm ox} }{\varepsilon _{\rm Si} }\frac{V_{\rm GS2}' -\phi _{\rm S2} (x)}{t_{\rm ox} }y \\& +\left\{ \frac{3+{2d\varepsilon _{\rm ox} }/{(t_{\rm ox} }\varepsilon _{\rm Si} )}{d^2}[V_{\rm GS2}'-\phi _{\rm S2} (x)]\right. \\& \left. -\frac{3(V_{\rm GS2}' +V_{\rm Sub} )}{d^2}\right\} y^2 \\& -\left\{ \frac{2+{2d\varepsilon _{\rm ox} }/ {(t_{\rm ox} \varepsilon _{\rm Si} })}{d^3}[V_{\rm GS2}'-\phi _{\rm S2} (x)]\right. \\& \left. -\frac{2(V_{\rm GS2}' +V_{\rm Sub} )}{d^3}\right\} y^3. \\ \end{split} \end{equation}$$ $

(10)

Substituting Eqs. (9) and (10) in Eq. (1), we get

$ $$\begin{equation} \frac{{\rm d}^2\phi _{\rm S1} (x)}{{\rm d}x^2}-\frac{6+4d\varepsilon _{\rm ox} /(\varepsilon _{\rm Si} t_{\rm ox} )}{d^2}\phi _{\rm S1} (x)= \frac{qN_{\rm A}}{\varepsilon _{\rm Si} }-\frac{4\varepsilon _{\rm ox} }{d\varepsilon _{\rm Si} t_{\rm ox} }V_{\rm GS1}', \end{equation}$$ $

(11)

$ $$\begin{equation} \frac{{\rm d}^2\phi _{\rm S1} (x)}{{\rm d}x^2}-\frac{6+4d\varepsilon _{\rm ox} /(\varepsilon _{\rm Si} t_{\rm ox} )}{d^2} \phi _{\rm S2} (x)=\frac{qN_{\rm A}}{\varepsilon _{\rm Si} }-\frac{4\varepsilon _{\rm ox} }{d \varepsilon _{\rm Si} t_{\rm ox} }V_{\rm GS2}' . \end{equation}$$ $

(12)

That is

$ \frac{{\rm d}^2\phi _{\rm S1} (x)}{{\rm d}x^2}-\alpha \phi _{\rm S1} (x)=\beta _1, \\ \frac{{\rm d}^2\phi _{\rm S2} (x)}{{\rm d}x^2}-\alpha \phi _{\rm S2} (x)=\beta _2, $

where $\alpha =\frac{6+4d\varepsilon _{\rm ox}/(\varepsilon _{\rm Si} t_{\rm ox} )}{{d}^2}$, $\beta _1 =\frac{qN_{\rm A} }{\varepsilon _{\rm Si} }-\frac{4\varepsilon _{\rm ox} }{d\varepsilon _{\rm Si} t_{\rm ox} }V_{\rm GS1}' $, $\beta _2 =\frac{qN_{\rm A} }{\varepsilon _{\rm Si} }-\frac{4\varepsilon _{\rm ox} }{{ d}\varepsilon _{\rm Si} t_{\rm ox} }V_{\rm GS2}'$.

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form

$ $$\begin{equation} \phi _{\rm S1} (x)=A\exp (\sqrt \alpha x)+B\exp (-\sqrt \alpha x)-\frac{\beta _1 }{\alpha}, \end{equation}$$ $

(13)

$ $$\begin{equation} \phi _{\rm S2} (x)=C\exp [\sqrt \alpha (x-L_1)]+D\exp [-\sqrt \alpha (x-L_1)]-\frac{\beta _2 }{\alpha}. \end{equation}$$ $

(14)

Equations (13) and (14) can be solved separately under the two gate regions using the following boundary conditions, i.e.,

(1) Surface potential at the interface of the two dissimilar polysilicons is continuous.

$ $$\begin{equation} \phi _1 (L_1, 0)=\phi _2 (L_1, 0). \end{equation}$$ $

(15)

(2) Electric flux at the interface of the two dissimilar polysilicons is continuous.

$ $$\begin{equation} \frac{{\rm d}\phi _1 (x, y)}{{\rm d}x}\Big|_{x=L_1 } =\frac{{\rm d}\phi _2 (x, y)}{{\rm d}x}\Big| _{x=L_1 }. \end{equation}$$ $

(16)

(3) The potential at the source start is

$ $$\begin{equation} \phi _1 (0, 0)=\phi _{\rm S1} (0)=V_{\rm bi} . \end{equation}$$ $

(17)

(4) The potential at the drain end is

$ $$\begin{equation} \phi _1 (L_1 +L_2, 0)=\phi _{\rm S2} (L_1 +L_2 )=V_{\rm bi} +V_{\rm DS} . \end{equation}$$ $

(18)

Solving Eqs. (15)-(18), we obtain the coefficients $A, B, C$ and D, i.e.,

$ $$\begin{equation*} \begin{split} A={}& \Big\{(V_{\rm bi} +\frac{\beta _2 }{\alpha }+V_{\rm DS} )-(V_{\rm bi} +\frac{\beta _1 }{\alpha })\exp [-\sqrt \alpha (L_1 +L_2 )] \\& +\frac{\beta _1 -\beta _2 }{\alpha }\frac{\exp (\sqrt \alpha L_2 )+\exp (-\sqrt \alpha L_2 )}{2}\Big\} \\& \times \left\{\exp [\sqrt \alpha (L_1 +L_2)]-\exp [-\sqrt \alpha (L_1 +L_2)]\right\}^{-1}, \end{split} \end{equation*}$$ $

$ $$\begin{equation*} \begin{split} B={}& \Big\{(V_{\rm bi} +\frac{\beta _1 }{\alpha })\exp [\sqrt \alpha (L_1 +L_2)]-(V_{\rm bi} +\frac{\beta _2 }{\alpha }+V_{\rm DS}) \\& -\frac{\beta _1 -\beta _2 }{\alpha }\frac{\exp (\sqrt \alpha L_2 )+\exp (-\sqrt \alpha L_2 )}{2}\Big\} \\& \times \left\{\exp [\sqrt \alpha (L_1 +L_2)]-\exp [-\sqrt \alpha (L_1 +L_2)]\right\}^{-1}, \end{split} \end{equation*}$$ $

$ C=A\exp (\sqrt \alpha L_1 )-\frac{\beta _1-\beta _2 }{2\alpha }, \\ D=B\exp (-\sqrt \alpha L_1 )-\frac{\beta _1-\beta _2 }{2\alpha}, $

and substituting A, B and C, D in Eqs. (13) and (14), we get the analytical surface potential.

3. Results and discussion

To verify the proposed analytical model, the 2-D device simulator MEDICI was used to simulate the surface potential distribution along the channel. The SMDWG structure is implemented in MEDICI having uniformly doped source/drain and body regions. The work function of S-gate is 5.25 eV, and the D-gate is 4.17 eV. The length of S-gate is $L_1$, the length of D-gate is $L_2$. All the device parameters are given in the figure captions.

In Fig. 2, the calculated and simulated values of surface potential are plotted against the horizontal distance in the channel with the channel length 90 nm for SMDWG MOSFET and single work function gate MOSFET. It is clearly seen that the SMDWG structure induces a step surface potential along the channel. Therefore, the electric field along the channel becomes more uniform and the electrons near the source are accelerated more rapidly. As a consequence, the average electron velocity in the channel is increased which results in higher carrier drift velocity and device speed. There is no such step profile in the surface potential in a single work function gate MOSFET. The model predictions are in good agreement with the simulation results.

In Fig. 3, the calculated and simulated values of surface potential are plotted against the horizontal distance in the channel with the channel length 90 nm for different drain voltages. It can be seen from the figure that due to the presence of the SMDWG, there is no significant change in the potential under the S-gate as the drain bias is increased with the channel length 90 nm. Hence, the channel region under S-gate is `screened' from the changes in the drain potential, i.e., the drain voltage is not absorbed under S-gate, but is under D-gate. As a consequence, it has only a very small influence on drain current after saturation and the drain conductance is reduced. It is evident from the figure that the shift in the point of the minimum potential is almost zero irrespective of the applied drain bias. This is a clear indication that the DIBL effect is considerably reduced for the SMDWG MOSFET. The model predictions are in good agreement with the simulation results.

In Fig. 4, the calculated and simulated values of surface potential are plotted against the horizontal distance in the channel with the channel length 90 nm for different values of oxide thickness for SMDWG MOSFET. According to the figure, the surface along the channel decreases as the oxide thickness increases. On the other hand, with increasing oxide thickness, S-gate and D-gate lose their control over the channel, which leads to an increase in the DIBL. Therefore, continuous scaling down of the oxide thickness reduces the DIBL but on the other hand, oxide thickness cannot be scaled down to very small values otherwise tunneling through the thin oxide and hot-carrier effects become prominent. The model predictions are in good agreement with the simulation results.

In Fig. 5, the calculated and simulated values of surface potential are plotted against the horizontal distance in the channel for different combinations of gate lengths $L_1 $ and $L_2 $ of S-gate and D-gate respectively, keeping the sum of total gate length, $L_1 +L_2$, to be 90 nm. It is seen from the figure that the position of minimum surface potential lying under S-gate is shifting toward the source as $L_1 $ decreases. This causes the peak electric field in the channel to shift more toward the source and thus there is a more uniform electric field profile in the channel resulting in higher carrier drift velocity and device speed. Moreover, it is observed that the channel potential minima for the three cases are not the same. This happens because as $L_1 $ increases, a portion of the channel controlled by the S-gate, which has larger work function, is increased. The longer $L_1 $ is, the smaller the minimum surface potential is. The model predictions are in good agreement with the simulation results.

In Fig. 6, the calculated and simulated values of surface potential are plotted against the horizontal distance in the channel with the channel length 90 nm for different substrate doping concentrations for SMDWG-MOSFET. According to the figure, the surface along the channel decreases as substrate doping concentration increases. The model predictions are in good agreement with the simulation results.

4. Conclusion

Based on the exact 2D solution of Poisson's equation, a new analytical surface potential model for the SMDWG MOSFET has been successfully developed. We have analyzed the influence of various device parameters on the device such as drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentrations. It is found that in the SMDWG MOSFET the step-function profile in the surface potential exhibits improvement in screening of the drain potential variation, and suppressed DIBL. The peak in the electric field distribution, under the gate, along the channel ensures more uniformity in the average drift velocity of the electrons in the channel. Furthermore, the shift in the zero-point electric field toward the source is negligibly small in SMDWG structure than in conventional single material gate structure. The model predictions are in good agreement with the simulation results proving the accuracy of our proposed analytical model.