Fig. 1.
Structure of the '$L$ -level' multiplier.
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| Citation: |
Xiaodan Guo, Qiao Meng, Yong Liang. A 4 GHz CMOS multiplier for sigma-delta modulated signals[J]. Journal of Semiconductors, 2014, 35(1): 015003. doi: 10.1088/1674-4926/35/1/015003
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X D Guo, Q Meng, Y Liang. A 4 GHz CMOS multiplier for sigma-delta modulated signals[J]. J. Semicond., 2014, 35(1): 015003. doi: 10.1088/1674-4926/35/1/015003.
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A 4 GHz CMOS multiplier for sigma-delta modulated signals
DOI: 10.1088/1674-4926/35/1/015003
More Information
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Abstract
An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier's noise performance is also presented.-
Keywords:
- CMOS,
- sigma-delta modulation,
- multiplier,
- bit-stream
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References
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