1. Introduction

With strict requirements of the latest wireless applications and wideband systems, it is intensive effort in developing highly integrated and low cost circuits. The monolithic microwave integrated circuit (MMIC) is a promising technology candidate for high integration and low costs, especially in modern communication and military microwave systems, where large quantities of radio frequency (RF) components are required.

Among the MMIC chips such as phase shifters^[1] and low noise amplifiers^[2], power amplifiers are the most attractive as the core components in transmitter modules. In fact, high power added efficiency (PAE), operation bandwidth and small size are the three characteristics required for power amplifier design. It is well known that high PAE can reduce the junction temperature and improve the thermal stability effectively. Most efforts have focused on improving the PAE of power amplifiers^{[3, 4]}.

The 6 to 18 GHz frequency band is widely used in many radar and commercial communication systems such as X-and Ku-band radars, ultra-wide-band and software-defined radios^{[5, 6]}. Therefore, lots of technologies have been adopted to design power amplifiers such as distribution structures^{[7, 8]} and stacked unit cells^[9]. However, the main obstacle to broadband power amplifier design is achieving high small signal gain, high PAE, wide band, and good voltage standing-wave ratio (VSWR), simultaneously. For instance, Chang et al.^[7] designed a distributed power amplifier with high PAE and a good VSWR, but the small gain is only about 10 dB, which is not enough for the phase array radar applications. In previous studies^{[10, 11]}, for > 30 dBm (> 1 W) output power, PAE is above 20% and $S_{11}$ is below –5 dB across 6–18 GHz. The low PAE means the large power dissipation, while the high $S_{11}$ causes serious mismatch at the input port. In this paper, a three-stage MMIC power amplifier has been designed, fabricated and tested. Over 6–18 GHz, the saturated output power ($P_{\rm sat})$ is about 32 dBm. PAE is improved to 28% and the input VSWR is below 2 : 1.

2. Circuit description

Various circuit techniques have been investigated in the design of wideband power amplifiers and they all depend on the performance of the active devices, such as GaAs, the PHEMT, and the HBT. HBT technology is utilized to design high-power MMIC chips because of its outstanding properties such as high output power density, and so on. However, the gain of HBT technology at high frequency is lower than that of PHEMT technology. Therefore, in consideration of the output power and gain, GaAs PHEMT technology is more suitable in this work.

The simplified circuit schematic is shown in Fig. 1. A three-stage circuit is adopted, and the gain of the MMIC power amplifier is about 23 dB. The final basic circuit is almost same as some other studies^{[12, 13]}.

The MMIC power amplifier is fabricated by using WIN PP15-20 processes. This technology has been optimized for high reliability and includes specific features for reducing the junction temperature and increasing the thermal stability of the device. An advanced design system (ADS) is utilized to simulate the MMIC performances. To achieve an accurate design, all the passive components, such as MIM capacitors, NiCr thin film resistors, microstrip lines, and so on, are considered by using an electromagnetic field simulator provided by ADS.

For each PA design, the first matching network is the output matching network in the output stage. Taken into account of the high output power, a large number of PHEMT cells are carried out in the output stage. In this study, it is composed of 4 unite cells, and the gate-width of each cell is 100 $\mu$m $\times$ 8. The load-pull result at 18 GHz is depicted in Fig. 2. The output power of each cell is 27.5 dBm, and the PAE is about 55%. The output network is designed to transfer maximum output power from the PHEMTs to a 50-$\Omega$ system. In this paper, the insert loss of the output network is only about 0.8 dB. After that, the interstage network is designed, which is utilized to provide additional slop gain compensation and change the impedance to the optimum input level for power matching of the output PHEMTs. In the interstage network, the scale of PHEMT is 75 $\mu$m $\times$ 8. Finally, the first stage is designed, which is not only for the input matching for the signal transferring to the next stage, but also can provide positive gain slop compensation. The scale of input cell is 50 $\mu$m $\times$ 8. The layout and simulated results are shown in Fig. 3. In the simulated results, the gain is about 24 dB. When input power is 12 dBm, the output power and PAE is above 32 dBm and 28%, respectively.

In general, the suitable matching network topology in the three stages is the key point to achieve the high output power. It must be a good compromise between power matching and low insertion loss. It has to be optimized for the maximal gain and the best flatness over the whole band. In order to prevent RF signals inferring with each other, lots of capacitors are inserted in the drain and gate path at each stage. The structures such as the capacitors to ground and long transmission lines are carried out to avoid the RF signal leakage into the power supply.

In fact, the simultaneous wideband matching and output power with good PAE optimization for the design is not easy to achieve. So some different circuit topologies are adopted in this work. In the interstage network, a transmission line instead of an inductor $L_{\rm m}$ is employed at the drain path of the transistors. It not only improves the matching conditions such as the gain and $S_{11}$, but also ameliorates the operation bandwidth. Maybe it results from the low quality factor of the inductor $L_{\rm m}$. In the output stage, a shunt capacitor $C_{\rm m}$ is used in the circuit as shown in Fig. 1. Because of $C_{\rm m}$, the length of the transmission line can be decreased effectively, which is good for lowering the insertion loss and decreasing the chip size. In addition, for the biasing network, some resistors and large capacitance are used to enhance the circuit stability and simplify the final chip layout.

3. Circuit implementation

The photograph of the three-stage MMIC power amplifier is shown in Fig. 4. The chip is compact with dimensions of 2.9 $\times$ 2.1 mm$^{2}$. The MMIC power amplifier is measured on the board as shown in Fig. 5. It is composed of the input and output SMA connectors and 50 $\Omega$ transmission lines. The MMIC power amplifier is connected to the PCB by bonding wires. The bonding wires are characterized by the lumped component model including very small DC loss, capacitance and large inductance as the function of length. The MMIC power amplifier is measured by Agilent network analyzer. The bias voltage of the MMIC power amplifier is shown in Table 1.

The measured results of small signal across the 6–18 GHz frequency range are shown in Fig. 6. The input power is only –30 dBm. Over 6–18 GHz, it is obvious that the input VSWR is below 2 : 1, and the output VSWR is below 3 : 1. The gain is about 23 $\pm$ 2 dB between 6–18 GHz. The differences between the simulated and measured results should be resulted from the variations in PHEMT fabrication processes, the mismatch from the jig and the loss from the SMA connectors. However, the gain fluctuation is lower than the previous studies^{[10, 11]}.

For the power measurements, since the output-power of network analyzer is not enough to drive the power amplifier, the driving amplifier is adopted. In this work, the driving amplifier is Agilent HMMC-5618 power amplifier. The details of the driver MMIC are described in Ref. ^[14]. The measured results are shown in Fig. 6. The input VSWR of the driving amplifiers is below 2 : 1, and the input power ($P_{\rm in}$ $=$ 0, 3 dBm) from the network analyzer is transferred to the driving amplifier. All the measurements are carried out under the continuous wave (CW) conditions. It is obvious that the $P_{\rm sat}$ is more than 32 dBm over 6–18 GHz as shown in Fig. 7(a). Even at 18 GHz, the $P_{\rm sat}$ is about 32 dBm. According to the measurements and HMMC-5618 data sheet, the PAE is calculated and shown in Fig. 7(b). The PAE between 6–18 GHz is about 28%, which is much higher than that in some papers^{[10, 11]}. In fact, a transmission line and a capacitor $C_{\rm m}$ are adopted in this study, so the loss and bandwidth of the circuits can be improved.

The performance of the presented amplifier is compared with other broadband power amplifiers as shown in Table 2. It demonstrates that the power amplifier has good performance, including PAE, small signal gain, input VSWR, and so on.

4. Conclusion

An MMIC power amplifier covering 6–18 GHz has been designed, fabricated and measured on the board. A three-stage circuit is adopted, and in order to improve the PAE and bandwidth, the transmission lines and shunt-wound capacitor $C_{\rm m}$ are provided in the interstage and output stage networks, respectively. According to the measured results, over 6–18 GHz, $P_{\rm sat}$ more than 32 dBm is achieved. Thus, the PAE is about 28% and input VSWR is below 2 : 1. The MMIC power amplifier with good efficiency and input match is suitable to be utilized in military and advanced communication systems.