1. Introduction

The recent growth of audio processing devices has increased the demand for an audio analog front-end (AFE) suited for portable use. There are quite a lot of key specifications for an AFE intended for battery-operated audio systems such as wearable speech devices, telephony, and hearing aids. Power dissipation directly effects battery life, so it must be as low as possible. Nowadays sub-1 V operation is required to use a common power supply with digital modules like digital signal processing (DSP) and memory, which already operate at very low voltage to reduce power consumption. A dynamic range of 70 dB is required for the AFE to be comparable with the quality of the audio signal. This paper presents the development of an audio AFE that meets these needs.

Realization of these performance goals involves both architectural and circuit-level considerations. On the architectural side, a closed-loop 30 dB-gain single-input PGA with 3 dB/step gain is adopted to amplify the weak audio signal. To ensure the stabilization of the circuit operation state, all the transistors of the PGA are working in the saturation domain instead of the sub-threshold domain. Multi-bit sigma-delta modulation offers several advantageous features for a low power audio AFE. The reduced quantization noise of the multi-bit quantizer allows a lower order of modulator for the same resolution compared with a modulator with a single-bit quantizer. The lower noise-shaping order simplifies the circuit design as well. In addition, smaller idle channel tones and less sensitivity to clock jitter make multi-bit quantization attractive for audio applications. The drawback of it is the nonlinearity of the internal digital-to-analog converter (DAC) that needs a dynamic element matching (DEM) technique to ease it. The data weighted averaging (DWA) technique falling in this category is adopted in this paper^{[1, 2]}.

A second key issue is the optimization of noise versus power efficiency at the circuit level. Although significant power savings can be achieved by proper allocation of the noise budget at the architecture level, efficiency of the AFE circuits becomes most critical at low voltage. Most notably, achieving a proper signal-to-noise ratio (SNR) becomes difficult with a reduced signal swing. To increase the power efficiency, two kinds of low-power operational transconductance amplifiers (OTA) are proposed for the PGA and multi-bit modulator respectively.

In this paper a low power, high performance audio AFE including the PGA and sigma-delta modulator have been integrated on a single 2.09 mm² chip fabricated in a 0.13-$\mu$m CMOS process. As a result of the power optimized PGA, the multi-bit sigma-delta architecture and the low-power circuit techniques, the AFE shows good power efficiency. The AFE achieves a 70-dB SNR over the 100-Hz to 20-kHz passband and consumes only 410 $\mu$W from a 1-V power supply. General system design considerations are described in Section 2. Section 3 focuses on the circuit design. The measured performance and conclusions follow in Sections 4 and 5.

2. AFE system design considerations

Former research revealed that a normal sound level varies from 60 dB SPL to 100 dB SPL in our daily life, which corresponds to a peak-to-peak amplitude of voltage from 1.25 to 125 mV. While the sound level that human talk and hearing usually ranges from 80 dB SPL to 90 dB SPL^[3-6]. So for these different sound levels, in order to ensure the normal reception of the human ear, the PGA gain must involve changes in a wide range: first, when the sound level is in the range of 60 dB SPL to 90 dB SPL, the PGA needs to provide 30-0 dB of gain; secondly, when the sound level is above 90 dB SPL, the PGA provides $-6$ to 0 dB attenuation of gain to protect the ears. So the gain dynamic range of the PGA is 36 dB, which varies from $-6$ to 30 dB by a 3 dB gain step.

Additionally, a 2nd-order 3-bit sigma-delta modulator and DWA technique are used to reduce both the power and the nonlinearity of the multi-bit DAC respectively. Because the 2nd-order modulator has only two OTAs, it consumes less power than high-order modulators. It also does not have the idle tone problem as in the 1st-order modulator. It is known that increasing the resolution of the quantizer has the important benefit that each additional bit of resolution in the quantizer yields an additional one bit or 6 dB of SNR. But the overall resolution of the multi-bit modulator is limited to the effective resolution of the multi-bit feedback DAC. In today's CMOS processes, it is difficult to build a DAC with better than ten bits of effective resolution because of the effects of random device mismatch. Therefore, our multi-bit sigma-delta ADC designs must rely upon some sort of DEM technique like DWA to increase the effective resolution of the feedback DAC^[7]. So with these considerations, the proposed AFE circuit in this paper is shown in Fig. 1.

3. Circuit designs

3.1 PGA

The PGA consists of two common-mode voltage bias circuits, the OTA and resistor array as Figure 1 shows. An audio signal is input to the PGA through a 1 μF capacitor that is used to eliminate the DC signal in the audio signal. The on-board capacitors $C_{\rm on\_board1}$ and $C_{\rm on\_board2}$ that are 1 $\mu$F are significant for filtering the power supply noise and stabilizing the 0.5 V voltage bias. In order to achieve the large input swing for the sigma-delta modulator, the PGA is designed as a fully differential structure to improve its output swing. Each common-mode voltage bias circuit is composed of the voltage-divided resistors from the power supply to the ground and the unity-gain buffer to provide 0.5 V voltage bias for OTA differential input.

In the 0.13 $\mu$m CMOS process and 1 V supply voltage, in order to ensure enough unit gain bandwidth and output swing, the main OTA of the PGA has a five-transistor 2nd-order structure with Miller compensation, as shown in Fig. 2. By using the PMOS input differential pair, the common-mode level of the OTA gets lower. Moreover, with their large width and length, the PMOS input differential pair can minimize the output noise due to its small 1/f noise, which means in the same output amplitude level, the dynamic range is improved^[8]. In this OTA, the ratio of $W/L$ of PM1 and PM2 are both 320 $\mu$m/1 $\mu$m.

To stabilize the output common-mode voltage of fully-differential OTA, a common-mode feedback (CMFB) circuit must be designed. The CMFB circuit in this paper is a 2nd-order OTA with Miller compensation and a two-stage CMFB circuit. In this structure, the second pole of the OTA is transferred from the drain of PM3/NM3 to the drain of PM4/NM4. The width and length of the transistors in the CMFB circuit are designed to be the same as the main OTA, so the first and second poles are very close. Since the third pole is located in the drain of PMC3/NMC3, which is also in the output stage of the CMFB circuit, it is decisive for the stabilization of the OTA design. In our design, by increasing the width of PMC3/NMC3, the third pole moves close to the first and second poles, which makes the acceleration of the roll off of the gain characteristic curve in a Bode plot. Finally the designed OTA demonstrates an 88-dB DC gain, a 20.8-MHz unity gain bandwidth, and a 71$^\circ$ phase margin for a 2-pF load.

In addition, within the allowed layout area, the common-mode input resistors and capacitors $R_{3}/R_{4}$ and $C_{3}/C_{4}$ should be greater. Because the $R_{3}/R_{4}$ is connected in parallel with the output impedance of the main OTA, which directly determines the DC gain. So lager $R_{3}/R_{4}$ can guarantee the OTA DC gain is almost unchanged with the CMFB circuit. The $C_{3}/C_{4}$ capacitance value determines the lower frequency of the AC signal. As a result, $R_{3}/R_{4}$ and $C_{3}/C_{4}$ are respectively for 500 K and 500 fF in this circuit.

3.2 2nd-order 3-bit sigma-delta modulator

In this paper, a 2nd-order 3-bit sigma-delta modulator structure with the DWA technique is used for low power and high resolution. A block diagram of the sigma-delta modulator is shown in Fig. 3, which consists of two integrators, a 3-bit quantizer, a 3-bit DAC, an encoder and the DWA module. The 3-bit DAC is a charge transfer structure and is composed of controlled switches and capacitors. Since the integral coefficient is the same as the feedback coefficient for both of the integrators, the sampling capacitor and the feedback capacitor are shared in integrators to reduce the chip area^[9]. Because the 3-bit quantizer structure includes seven comparators, the load of the second integrator output is still heavy. For sufficient drive ability, the same OTA is used in two integrators.

To get high DC gain and a large output swing, an OTA with a cross-coupled active load and two-stage structure is designed for the modulator. By using PMOS input differential pair, the 1/f noise is reduced and the common-mode input level can be lower. The output of the switch-capacitor common mode feedback (SC-CMFB) under control of clk1 and clk2 is fed back to the gate of PM3 and PM4 for holding the 0.5 V output common-mode voltage. In simulation, the OTA demonstrates a 70-dB gain, 10 MHz GBW, more than a 60$^\circ$ phase margin for a 2-pF load. The circuit of the OTA and SC-CMFB is shown in Fig. 4.

In a sigma-delta modulator, the 3-bit quantizer is adapted from a 3-bit CMOS flash ADC architecture, which includes seven comparators. The 3-bit quantizer finally outputs complementary thermometer codes Y[6:0] and YB[6:0] to the encoder and the DWA module.

For fast operation, the DWA module must complete its operation before the switch-capacitor sampling edge. It is significant to prevent kickback noise among comparators. So the comparator circuit is designed to combine a high regeneration speed with a low offset and kickback noise, as shown in Fig. 5. The comparator circuit consists of two input pairs of PMOS (M3/M4, M5/M6), CMOS latch (M7-M12, M16/M17) and SR latch. NMOS transistor M14 is the reset switch, and M13 and M15 as assistant transistors are used to reduce the impact of charge injection when M14 is on. Clk and clkb are two-phase and non-overlapping clock signals. During the clock phase clk, the reset switch is on, the top and bottom regeneration loop are reset and the input differential pairs inject a current, which generates an initial voltage imbalance. In clock phase clkb, this imbalance determines the outcome and accomplishes the comparison.

DWA is a DEM technique which reduces the matching-requirements of the DAC unity elements. The DWA algorithm use elements at the maximum possible rate to ensure that the DAC errors will quickly sum to zero, which means converting the noise and distortion introduced by the non-ideal DAC into a first order high-pass noise shaped error^[2]. The main advantage of the DWA algorithm is its simplicity for use. It uses all the DAC elements at the maximum possible rate while ensuring that each element is used the same number of times. This is done by sequentially selecting elements from an array, beginning with the next available unused element. Figure 6 illustrates the concept for a 3-bit DAC with an input sequence of 0000010, 0000100, 0000101, 0000001 and 0000010.

As shown in Fig. 7, the DWA circuit consists of an 8-3 encoder, a full adder, a cycle log-shifter, a register and a timing adjust/driver. The shifter operating structure of the full adder and log-shifter is optimized for minimum delay in the feedback-path of the sigma-delta modulator. It is also beneficial for saving the power consumption of the DWA module^[2]. The DWA module is controlled by clk and clkb, which are two-phase and non-overlapping clock signals. One path of 3-bit data of the modulator is encoded and output by the encoder as an ADC output code. Another is added to the modulator output a clock cycle before. The rotation pointer is stored in the register when the full adder outputs S1-S3 and sends them to the register in the period of clkb. After that, S1-S3 control the cycle log-shifter to shift correspondingly. Finally, the timing adjust/driver improves the driving capability of the shifter signal and outputs the switch-selected signal Out_to_DAC[6:0].

4. Experiment results

The AFE is fabricated in SMIC 0.13 $\mu$m 1P8M CMOS technology with a 1 V voltage supply. The chip microphotograph is shown in Fig. 8. The area is 2.09 mm$^2$ (1.1 $\times$ 1.9 mm$^{2})$.

After tapeout, the SNR performance of the AFE is measured with different signal amplitudes. When the frequency of the input signal is 2.1 kHz, the PGA gain is set as 30 dB, 12 dB, and output voltage amplitude is 200 mVp-p, the SNR$_{\rm peak}$ is 70 dB. The output spectrum is shown in Fig. 9, which shows that even in a 1 V supply voltage, the circuit shows a high performance of output resolution.

Figure 10 shows the measured SNR as a function of the input signal.

The measured performance of the proposed analog front-end is summarized in Table 1.

Table 2 compares the performance of the proposed AFE circuit with that of previous works. The proposed AFE shows 70 dB SNR at a power supply voltage of 1 V that is comparable with other works.

5. Conclusions

A 410 $\mu$W, 70 dB SNR high performance analog front-end for portable audio application is proposed and implemented in the SMIC 0.13 $\mu$m 1P8M CMOS process. Special attention is paid to the low power, high dynamic range OTA design both for the PGA and the sigma-delta modulator. Measurement results show that in a 1 V power supply, between the bandwidth of 100 Hz and 20 kHz, the SNR$_{\rm peak}$ is 70 dB, with the bandgap and the LDO circuit, the total power is 410 $\mu$W. Therefore, our design satisfies the requirement of the intended portable application of audio signals.

There are still two aspects of our work that need to be improved in the future. First, the sub-threshold transistors may be designed in our circuits, which may be the substitutes for transistors in the saturation domain and they will realize the power consumption under 100 $\mu$W after careful design. Second, the continuous-time sigma-delta modular structure may be adopted both to ensure the performance of the AFE and optimize the power consumption, because the OTAs of it will consume much less current for its limited unit gain-bandwidth compared with those in the switch-capacitor modulator.