1. Introduction

Mixed-signal microcircuits are increasingly found in the applications of space systems that have been subjected to radiation. As one type of clear mixed signal device, analog-to-digital converters (ADCs) are critical interface circuits between the analog and digital parts, so it is important to research the total ionizing dose (TID) effects of ADCs. The effects of the TID and the dose rates of ADCs have been studied since the 1990s by agencies such as JPL and NASA^[1-5]. However, all the researched objectives had low sample rates. Now, researchers at the Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences have performed some studies on ADCs^{[6, 7]}, although only the DC parameters were tested and analyzed. Other domestic agencies have also done some evaluation experiments, but did not analyze the damage mechanism.

Many of the applications of ADCs require an improved sample rate and accuracy. In modern high sample rate ADCs, conventional DC parametric measurements are not always sufficient to characterize the performance of ADCs. Therefore, the AC parameters need to be tested because the AC specifications are important for communication applications such as spectrum analysis and digital signal processes. Moreover, the application of ADCs is different in normal and power-down modes. In normal mode, the input signal is different with different applications, so it is also important to study the different biases. On the other hand, modern high-speed and high-resolution ADCs are often fabricated by sub-micron, even nano CMOS processes, and the complex architectures are also different from older ADCs. As we all know, shallow trench isolation (STI) was introduced at the 0.25 $\mu$m technology node to reduce spacing between adjacent devices compared to the LOCOS isolation process. According to recent research, increased damage at a low dose rate in some sub-micron CMOS processes has been found^{[8, 9]}. So what about mixed-signal integrated circuits? And we do not know whether the failure mode is the same as in older ADCs or not?

This paper discusses the results for both different biases and dose rates on modern CMOS technology, 12-bit, 125 MSPS ADCs from the manufacturer Analog Devices. According to the experimental results, we recognize the failure mode and worst-case bias. We also perform some mechanism analysis and discuss the radiation damage.

2. Device and experimental setup

2.1 Device description

AD9233 is a monolithic, single 1.8 V supply, 12-bit, 125 MSPS ADC, featuring a high-performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses multistage differential pipeline architecture with correction logic and output buffer blocks. The output buffer block needs a separate supply to accommodate 1.8 to 3.3 V logic families.

2.2 Testing system setup

Electrical testing is performed using the self-setup system, which combines an analog signal generator (SMA100A), low noise power (E3631), a logic analyzer (TLA5203B) and an evaluation board specially built to test AD9233. After sampling the output codes of AD9233, we calculate: (1) DC parameters such as differential nonlinearity (DNL) error, integrated nonlinearity (INL) error, and Misscode. (2) AC parameters such as signal-to-noise-ratio (SNR), signal-to-noise and distortion (SINAD), total harmonic distortion (THD), spurious-free dynamic range (SFDR), and the effective number of bits (ENOB). Evaluation board layout and input signal filtering are critical issues to be dealt with. Coaxial cables are used to interface the analog and clock signals. Finally, in the whole testing system, the test fixture is also very important. It can influence the performance of the electrical parameters, especially the AC parameters. In this paper, we choose the test fixture manufactured by Plastronics. With or without it, the influence is about several dBs. However, of concern to us are the changes pre-and post-irradiation. So we can ignore the influence of the test fixture only if the testing system can finish the electrical testing with it. The electrical testing was performed with the device configured as shown in Table 1.

2.3 Experimental conditions

The irradiation experiments were performed for the devices using a $^{60}$Co $\gamma$-ray irradiator from the Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, at a high dose rate of 62.76 rad(Si)/s and a low dose rate of 0.54 rad(Si)/s. After all irradiation was completed, the devices irradiated at a high dose rate were annealed with the same biases at room temperature for 72 h. According to the application background, we chose some bias types, as shown in Table 2. For the experimental products, four chips were prepared for the total dose and tested under each condition, and another chip was used as the control device. All the samples performed an offline test, regardless of irradiation or annealing on the testing system according to "General principles of measuring methods of A/D and D/A converters for integrated circuits".

3. Experimental results

The AC and DC parameters mentioned previously were measured pre-and post-irradiation, and post-annealing. Some parameters were sensitive and others were not. The data were analyzed to observe the degradation of each of these sensitive parameters as a function of the total dose and annealing time. The results for these parameters are presented in the following figures.

3.1 Radiation response for different biases

The most sensitive parameter was the power-down current. Figure 1 shows the radiation response of this at different total doses under four conditions. According to Fig. 1, the power-down current first increased with increasing total irradiation dose, and then the conversion function of the ADC failed when it increased to a certain value. We also found that the three other conditions, except for power down, remained functional at 80 krad(Si), so the power-down bias was the worst-case condition. Moreover, no noticeable differences were found with different input conditions under a normal operating state. The failure level was 130 krad(Si) under dynamic input, 140 krad(Si) under DC 2 V input, and 160 krad(Si) under DC 0 V input.

Figure 2 describes the relationship between INL, one of the most important DC parameters, and total dose under different biases. No changes were observed before functional failure occurred, which means that this was a disastrous failure mode. The damage behaviors were the same whatever the INL+ or INL-. Another parameter that showed significant changes in radiation degradation was SNR, as shown in Fig. 3. Like INL, SNR was also within the specification before function failure happened. Although SNR had a slight degradation after 80 krad(Si) at dynamic and static ($V_{\rm in}$ $=$ 0 V) biases, it was still within its specification. Contrasting Figs. 1, 2 and 3, we found that the current showed an increase in gradient, whereas the functional parameters including AC and DC had disastrous failures. Other sensitive parameters such as DNL, SINAD, THD, ENOB, and Misscode had the same TID characterization as INL and SNR, and we do not discuss them here.

3.2 Dose-rate effects

As we all know, the increased damage at low dose rates that occurs in bipolar linear devices has been widely studied. The dose-rate effects in scaled CMOS were reported by Zebrev and co-workers^[9]. They observed low dose-rate effects in the shallow trench isolation regions on the drain current. However, the dose-rate effects on integrated circuits fabricated on modern CMOS processes have not been reported. The results of different dose rates on AD9233 are shown in Fig. 4. Figure 4(a) describes the relationship between the power-down current and the total dose under different biases and dose rates, and Figure 4(b) shows the annealing characterization at room temperature. According to Fig. 4(a), the power-down current did not change at a low dose rate, and we also found that the power-down current recovered to its initial value quickly in the first few hours, reaching its initial value at 24 h, as shown in Fig. 4(b). No enhanced irradiation damage was observed during room-temperature annealing. Other radiation-sensitive parameters, including the DC and AC parameters, displayed the same annealing behaviors. In this experiment, no low dose-rate effect was found.

3.3 Other parameter results

The other test parameters of pre-and post-radiation, and post-annealing are shown in Table 3. We can see that VREF and IREF were within the specifications during all the experimental processes. IAVDD and IDRVDD showed a slight increase after irradiation. Moreover, all these parameters recovered to the initial values during the subsequent room-temperature annealing experiment.

4. Analysis and discussion

For older CMOS processes, the shift in threshold voltage and the increased leakage current are the two major irradiation damage phenomena. However, the degradation on the threshold voltage can be ignored in modern CMOS processes^[10]. According to the recent literature, radiation-induced leakage current exhibits significant sensitivity to TID effects^[10-13]. The radiation-induced excess leakage current includes intra-and inter-leakage currents, as shown in Fig. 5. Both these currents were caused by the oxide trapped charge in the STI and then inverted the channel. This increasing leakage current makes the transistors remain in the ON state and this cannot be shutdown. This is fatal in digital integrated circuits, but otherwise this damage will not influence the analog integrated circuits because they always operate in the saturation region of the transistors and the leakage current is small compared to the saturation region drain current.

As mentioned in Section 2, the AD9233 architecture consists of a front-end SHA followed by a pipeline-switched capacitor ADC, a digital correction logic circuit, a reference circuit, and so on. Each stage of the pipeline, excluding the final one, consists of a low-resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier. The final stage simply consists of a flash ADC. According to the experimental results, we know that the reference, amplifier, biasing networks and output drivers function well during the experiments. So the sensitive blocks could be flash ADC and digital correction logic blocks.

As we all know, a simple flash ADC architecture generally combines comparators and decodes logic circuits, as shown in Fig. 6. Either a shift in the input offset voltage resulting from the threshold voltage shifts, or a functional failure in the decode logic circuit caused by increasing edge leakage current could bring about the functional failure of AD9233. In addition, digital correction logic circuits are composed by combination and sequential logic circuits such as D flip-flops and decoders^[14]. Any degradation of these logic circuits will cause ADC function failure. Typically, all of these logic circuits include NOR gates, NAND gates, and inverters. In a typical NOR circuit, the leakage in the parallel N-channel transistors will significantly load the series P-channel transistors when the output is in a "1" state. If the output is not able to maintain a solid "1" state, logic error may be generated. A similar failure will also happen in the other logic circuits.

For the power-down bias, the reference, reference buffer, biasing networks and clock were shut down and the output drivers placed in a high impedance state. In this situation, the transistors of the remaining blocks that were not shut down may be in the worst-case condition. And for the other three biases, the transistor states might constantly change. This is why the power-down bias was the worst-case condition. No matter what kind of bias, there is no enhanced low dose-rate sensitivity effect, according to Fig. 4. This phenomenon means that no interface-trapped charges were produced during irradiation, and the oxide-trapped charges produced on the high dose rate were neutralized by the electron or H$^{+}$ at room-temperature annealing.

5. Conclusions

We presented a comprehensive experimental study of the radiation response of a high-speed and high-resolution ADC. The power-down current is the most sensitive parameter, and power down is the worst-case bias. The failure mode is functionally disastrous failure because of failure on the logic circuits resulting from an increase in radiation-induced leakage current. By comparing the experimental results of different dose rates and annealing behaviors, all the parameters and the conversion function show time-dependent effects, and no low dose-rate effects were observed.

For high-speed and high-resolution ADCs, it is hard to evaluate and analyze the degradation mechanisms because of the complicated structure and massive blocks inside. In this experiment, we obtained an elementary result and analyzed the degradation mechanisms preliminarily. We now plan to design some experiments to research MOS transistors, block units and ADCs. All these parts are fabricated on the same process line, so it is possible to study the degradation mechanisms more thoroughly and accurately.