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J. Semicond. > 2014, Volume 35 > Issue 9 > 094008

SEMICONDUCTOR DEVICES

The expression correction of transistor current gain and its application in reliability assessment

Haochun Qi1, 2, , Xiaoling Zhang1, Xuesong Xie1, Li Zhao1, Chengju Chen1 and Changzhi Lü1

+ Author Affiliations

 Corresponding author: Qi Haochun, Email:jetqi@sina.com

DOI: 10.1088/1674-4926/35/9/094008

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Abstract: Considering the impacts of ideal factor n, VBE and band gap changes with the temperature on current gain, the current gain expression has been corrected to make the results closer to the actual test. Besides, the accelerating lifetime study method in the constant temperature-humidity stress is used to estimate the reliability of the same batch transistors. Applying the revised findings from the expression, the current gains before and after the test are compared and analyzed, and, according to the degradation data of the current gain, the transistor lifetimes in the test stress are respectively extrapolated in the different failure criteria.

Key words: bipolar transistorstemperature featurecurrent gainaccelerating lifetime

A component's reliability is associated with the stability of its electrical parameters in different environments, among which the transistor's common-emitter current amplification factor, the current gain hFE, varies with the temperature and influences the performance and reliability of transistors. Thus it is significant to study and analyze the relationship between the current gain and the temperature. Research has shown that the temperature features of the current gain are mainly related to the following factors: the band gap narrowing caused by being heavily doped in the emitter region, the relationships between the mobility, other physical quantities and the temperature, the ideal factor of the base current is not 1[1, 2], the high current injection effect and other factors[3]. Based on the studies above, in this paper, the ideal factor, VBE and band gap changes with the temperature are studied and analyzed, and the current gain expression is corrected to make the results closer to the actual test.

In addition, the accelerating lifetime study method in the constant temperature-humidity stress is used to estimate the reliability of the same batch transistors. Applying the revised findings from the expression, the current gains before and after the test are compared and analyzed. Then, according to the degradation data of the current gain, the transistor lifetimes in the test stress are respectively extrapolated in the different failure criteria.

It is known that the temperature model of current gain hFE can be represented by the following formula[4, 5]:

hFE=NEμBWENBμEWBexp(ΔEgkT).

(1)

In Eq. (1), NE, μE, WE are respectively the impurity concentration in the emission region, the minority carrier mobility and emission region width, NB, μB and WB are respectively the impurity concentration in the base region, the minority carrier mobility and the base region width, and ΔEg are the relative band gap narrowing values in the emission and base regions caused by the heavy doping[5]. As the base region generally uses light doping, its band gap narrowing value can be negligible. Thus ΔEg is determined by the band gap narrowing value in the emission region.

It is known that the ideality factor n contains the non-ideal element impacts from the barrier region, the surface recombination current and the base current. The subtle difference between n and 1 may influence the transistor's electrical characteristics a little, so it is also not noticed and it is generally thought that n= 1. However, the tests have verified the n's impact on the temperature characteristics hFE cannot be ignored, even in the medium current range, the objective fact n > 1 should be considered[1]. Therefore, the impact of the ideal factor of the base current n 1 on the current gain needs to be considered, and its relationship between the current gain and the temperature can be converted into:

hFE=NEμBWENBμEWBexp(ΔEgkT)exp[(11n)qVBEkT].

(2)

Equation (2) comprehensively reflects the impacts from both the heavy doping ΔEg and base current ideality factor n on the current gain. The band gap narrowing effect caused by the heavy doping in the emission makes hFE have the significant positive-temperature coefficient characteristics. The base current ideality factor n is not equal to 1, which makes the exp[(11n)qVBE/kT] also have a negative-temperature coefficient and further weakens the impact of the band gap narrowing effect on hFE.

By the test, the current gain features are analyzed. 3DK105B transistors are selected as the test samples, taking a temperature point at 10 K intervals (totally 19 temperature points) between 218 K and 398 K (65 to 125 ℃) to test the current gain changes with the IC and BE junction forward characteristics. The test conditions are: VCE = 1 V and IC = 10 mA. The test equipment is the semiconductor parameter analyzer KEITHLEY 4200-SCS. The test environment temperature is controlled within 25 ± 3 ℃, and the humidity within 50 ± 5% RH. The whole test is conducted in a shielded room in order to reduce the external interference on the test results. The temperature control equipment is the high precision incubator DESPATCH, whose temperature control accuracy can reach ±0.5 ℃, using the liquid nitrogen refrigeration to realize the experimental low-temperature control.

The parts of the hFE-IC test results at the various temperature points are shown in Fig. 1.

Figure  1.  The hFE-IC curve at different temperatures

Choosing hFE when IC = 10 mA and the temperature point T = 298 K (room temperature 25 ℃) as the datum point, the test results of the current gain are normalized, which is shown in Fig. 2.

Figure  2.  The actual test curve of normalized current gain

By the craft of 3DK105B transistors, it is known NE/NB = 100, and WE/WB = 7/15. For the silicon devices, the relationship between its mobility and the temperature[6] is: μB T2.3±0.1, μET2.2±0.1. Thus it can be seen that μB/μE=T0.1.

For the silicon material transistors, the ΔEg empirical formula[7] is:

ΔEg=3.4×108(N13DN13d).

(3)

In Eq. (3), Nd =1.85 × l015 cm3, ND means the donor impurity concentration.

In terms of the craft of 3DK105B transistors, we can get: ΔEg = 0.068 eV.

Through the transistor samples test, when choosing IC = 10 mA, the corresponding n = 1.033 and VBE = 0.575 V, which is brought into Eq. (2). The curve of the formula results is normalized (Fig. 3(b)), and is compared with that of the actual test results (Fig. 3(a)), as shown in Fig. 3.

Figure  3.  The compared curves between Eq. (2) normalized results and the actual test normalized results

When T = 398 K, the actual test normalized result hFE(T)/hFE(T0) = 1.57, and Equation (2) normalized result hFE(T)/hFE(T0) = 1.43.

When T = 218 K, the actual test normalized result hFE(T)/hFE(T0) = 0.53, and Equation (2) normalized result hFE(T)/hFE(T0) = 0.59.

From Fig. 3, it is seen that the higher the temperature, the larger the differences between the Eq. (2) results (n = 1.033, VBE = 0.575 V) and the actual test ones. In order to more accurately reflect the current gain changes with the temperature, the effects of temperature changes on n and VBE need to be considered.

With the current relationship of the PN junction I=I0expqVBEnkT, the ideal factor n=dVdlnIqVBEkT can be achieved. According to the BE junction forward I-V feature curve, IB and the corresponding VBE are obtained, so the ideality factor n at different temperature points can be calculated. The changes of VBE and n with the temperature are shown in Fig. 4.

Figure  4.  The curves of VBE and n changes at different temperatures

Figure 5 respectively shows three normalized curves: one of Equation (2) considering VBE and n changes with the temperature (Fig. 5(a)), one of the actual test results (Fig. 5(b)), and one of Eq. (2) not considering VBE and n changes with the temperature (Fig. 5(c)).

Figure  5.  The comparing cures of actual test normalized results and Eq. (2) normalized results in different conditions

At the different temperature points, the test conditions of current gain are VCE = 1 V and IC = 10 mA. For different temperature points, the corresponding base current IB also changes. Therefore, n and VBE also change with the temperature. It can be seen from Fig. 5, Eq. (2) results are much closer to the actual test (Fig. 5(a)), for it considers VBE and n changes with the temperature (Fig. 5(b)).

In order to more accurately calculate the current gain changes with the temperature, the impact of the band gap changes with the temperature on the current gain needs to be considered. Equation (2) does not take this into account, so it cannot fully reflect the current gain changes with the temperature. Thus Equation (2) needs to be corrected. Reference [6] points out its empirical formula is:

ΔEg=αT2T+β,

(4)

where α = (4.73 ± 0.25) × 104 eV/K, and β = 636 ± 50 K. ΔEg is the change amount caused by band gap narrowing changes with the temperature.

Considering the band gap changes with the temperature, the corrected Eq. (2) can be inverted into:

hFE=NEμBWENBμEWBexp(ΔEgkT)×exp[(11n)qVBEkT]exp(ΔEgkT).

(5)

Figure 6 respectively gives three normalized results: the actual test one (Fig. 6(a)), an Eq. (2) one considering VBE and n changes with the temperature (Fig. 6 (b)), an Eq. (2) one not considering that (Fig. 6(c)) and an Eq. (4) one (Fig. 6(d)).

Figure  6.  Comparison curves of the actual test normalized results, Equation (4) normalized results and Equation (2) normalized results in different conditions

Because NEuBWENBuEWB in Eq. (4) has a negative temperature coefficient, it partially compensates the heavily doped effects on the temperature features of bipolar transistors. The index item exp[(11n)qVBEkT] considers two influences on the current gain: one is the ideal parameter of the base current n which is not 1, and the other is n and VBE change with the temperature. The item exp(ΔEgkT) considers the effect of band gap changes with the temperature on the current gain. Therefore, it can be seen from Fig. 6, that the Eq. (4) normalized curve (Fig. 6(d)) is closer to the actual test one (Fig. 6(a)).

When analyzing the temperature features of bipolar transistor current gain, such factors should be considered: the band gap narrowing caused by being heavily doped in the emitter region, the relationships between the mobility, the other physical quantities and the temperature, the impact of ideal factor n which is not 1, and the effects of the ideal factor, VBE and the band gap changes with the temperature. Only when all these factors above are considered comprehensively, can the temperature features of the current gain be analyzed more accurately. In addition, the base region is much smaller than its minority-carrier diffusion length, whose impact on the current gain hFE is also very important. However, this needs further study in the future, so it will not be illustrated here.

Selecting 10 3DK105B bipolar transistors as the study object, which are all from the same batch as the previous tests, Equation (4) is tested. The findings show the normalized curve by Eq. (4) is much closer to the actual test one, which indicates the preceding conclusions have universality.

The test conditions are divided into three groups where: the constant temperature is 100 ℃ and the constant humidity is 100% RH; the constant temperature is 90 ℃ and the constant humidity is 90% RH; the constant temperature is 65 ℃ and the constant humidity is 95% RH. Every group uses 10 samples, and their cumulative test times are respectively 2800, 3800 and 4500 h. At a certain test interval, the electrical parameters of samples are tested. Combining the corrected current gain theory discussed above, after the analyses of current gain before and after the test, it is found that it tends to decline. Table 1 states the current gain values of 10 transistor samples before and after the test in the conditions where the constant temperature is 100 ℃ and the humidity is 100% RH.

Table  1.  hFE data of transistors before and after the test
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Changes of transistor parameters are almost related to the temperature. In the function of the temperature, movable ionic charges in the oxide layer of interface Si-SiO2 can both vertically and horizontally move, so that the number and location of negative charges in interface Si also change, which causes the drift of the current gain. Besides, interface traps can also simultaneously capture an electron and hole, playing the role of a recombination center, which results in the reduction of the current gain of the device[8, 9].

Choosing transistor 10 as the example, Table 2 shows the corresponding hFE degradation data at various test times. Its degradation data is fitted (as shown in Fig. 7), and its lifetime in the temperature of 100 ℃ and humidity of 100% is extrapolated in different criteria.

Table  2.  hFE degradation of transistor Number 10
DownLoad: CSV  | Show Table
Figure  7.  hFE degradation fitting curve of transistor 10

Taking transistor 10 as the example, the corresponding degradation data of hFE at the different test times are stated in Table 2, which are fitted (as shown in Fig. 7), and the samples' lifetimes at the various criteria are extrapolated in 100 ℃ and comparative 100% RH.

Taking a 25% decrease of the current amplification coefficient hFE as the failure criteria, the lifetime of transistor 10 in the 100 ℃ and 100% RH stress is extrapolated. Table 3 states the extrapolated lifetimes results in the three tests.

Table  3.  Extrapolated lifetimes of test samples at three groups
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The current amplification coefficient hFE reduces by 20%, 25% and 30%, which is taken as the failure criteria to extrapolate the lifetime of Transistor 10 in 100 ℃ and comparative 100% RH stress, as shown in Table 3.

The maximum likelihood estimation method is used to estimate the parameters; the K-S goodness of fit test is applied to analyze the extrapolated lifetimes in Table 4. As shown in Table 4, the goodness of fit tests and parameter estimation in several common distributions are presented.

Table  4.  Parameter assessment in three common distributions
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From Tables 3 and 4, it is seen that, in the test condition and failure criteria, the lifetimes of transistors are extrapolated from their sensitive parameters, which are within 103 to 104. Besides, in terms of the above, the current gain degradation conforms to the power law, which is similar to the results given by Chen, Bravo, Lloyd and others[9-12].

In this paper, the current gain expression is corrected, which is also verified by the test, to make the results closer to the actual test. It is found in the research, the analyses of temperature features of bipolar transistor current gain should consider the following factors: the band gap narrowing caused by being heavily doped in the emitter region, the relationships between the mobility, the other physical quantities and the temperature, the impact of ideal factor n which is not 1, and the effects of the ideal factor, the VBE and the band gap changes with the temperature. Besides, applying the revised findings from the current gain expression, the accelerating lifetime study method in the constant temperature-humidity stress is used to estimate the reliability of the same batch of transistors.



[1]
Li Xuexin, Lin Yayun. Investigation of current-gain temperature dependence in bipolar transistors. Acta Electronica Sinica, 1984, 5:45
[2]
Li Zhiguo, Cheng Yaohai, Sun Yinghua, et al. The analysis of bipolar transistor hFE failure under low temperature and its reliability in application. Journal of Beijing Polytechnic University, 1996, 4:25
[3]
He Jian, Xu Xueliang. Study on temperature effects on current gain of bipolar transistor. J Microelectron, 2012, 2:270
[4]
Zheng J, Wu J, Wei T. Silicon bipolar transistors with temperature stable current gain. J Electron Devices, 1991, 1:44
[5]
Gao Guangbo, Li Xuexing. Semiconductor device reliability physics. Science Press, 1987:71
[6]
Pierret R F. Semiconductor device fundamentals. 2nd ed. Addison Wesley, 1996
[7]
Vol'fson A A, Suvashiev V K. Fundamental absorption edge of silicon heavily doped with donor or acceptor impurities. Sov Physics Semiconductors, 1961, 1:327
[8]
He M, Li H F, Wang P I, et al. Bias temperature stress of Al on porous low-k dielectric. Microelectron Reliab, 2011, 51(8):1342 doi: 10.1016/j.microrel.2011.03.004
[9]
Qi Haochun, Lü Changzhi, Zhang Xiaoling, et al. Accelerating the life of transistors. Journal of Semiconductors, 2013, 34(6):064010 doi: 10.1088/1674-4926/34/6/064010
[10]
Zhao L, Tokei Z, Croes K, et al. Direct observation of the 1/E dependence of time dependent dielectric breakdown in the presence of copper. Appl Phys Lett, 2011, 98:032107 doi: 10.1063/1.3543850
[11]
Lloyda J R, Liniger E, Shaw T M. Simple model for time-dependent dielectric breakdown in inter-and intralevel low-k dielectrics. J Appl Phys, 2005, 98:084109 doi: 10.1063/1.2112171
[12]
Chen F, Bravo B, Chanda K, et al. A comprehensive study of low-k SiCOH TDDB phenomena and its reliability lifetime model development. Proceedings of International Reliability Physics Symposium, 2006:46
Fig. 1.  The hFE-IC curve at different temperatures

Fig. 2.  The actual test curve of normalized current gain

Fig. 3.  The compared curves between Eq. (2) normalized results and the actual test normalized results

Fig. 4.  The curves of VBE and n changes at different temperatures

Fig. 5.  The comparing cures of actual test normalized results and Eq. (2) normalized results in different conditions

Fig. 6.  Comparison curves of the actual test normalized results, Equation (4) normalized results and Equation (2) normalized results in different conditions

Fig. 7.  hFE degradation fitting curve of transistor 10

Table 1.   hFE data of transistors before and after the test

Table 2.   hFE degradation of transistor Number 10

Table 3.   Extrapolated lifetimes of test samples at three groups

Table 4.   Parameter assessment in three common distributions

[1]
Li Xuexin, Lin Yayun. Investigation of current-gain temperature dependence in bipolar transistors. Acta Electronica Sinica, 1984, 5:45
[2]
Li Zhiguo, Cheng Yaohai, Sun Yinghua, et al. The analysis of bipolar transistor hFE failure under low temperature and its reliability in application. Journal of Beijing Polytechnic University, 1996, 4:25
[3]
He Jian, Xu Xueliang. Study on temperature effects on current gain of bipolar transistor. J Microelectron, 2012, 2:270
[4]
Zheng J, Wu J, Wei T. Silicon bipolar transistors with temperature stable current gain. J Electron Devices, 1991, 1:44
[5]
Gao Guangbo, Li Xuexing. Semiconductor device reliability physics. Science Press, 1987:71
[6]
Pierret R F. Semiconductor device fundamentals. 2nd ed. Addison Wesley, 1996
[7]
Vol'fson A A, Suvashiev V K. Fundamental absorption edge of silicon heavily doped with donor or acceptor impurities. Sov Physics Semiconductors, 1961, 1:327
[8]
He M, Li H F, Wang P I, et al. Bias temperature stress of Al on porous low-k dielectric. Microelectron Reliab, 2011, 51(8):1342 doi: 10.1016/j.microrel.2011.03.004
[9]
Qi Haochun, Lü Changzhi, Zhang Xiaoling, et al. Accelerating the life of transistors. Journal of Semiconductors, 2013, 34(6):064010 doi: 10.1088/1674-4926/34/6/064010
[10]
Zhao L, Tokei Z, Croes K, et al. Direct observation of the 1/E dependence of time dependent dielectric breakdown in the presence of copper. Appl Phys Lett, 2011, 98:032107 doi: 10.1063/1.3543850
[11]
Lloyda J R, Liniger E, Shaw T M. Simple model for time-dependent dielectric breakdown in inter-and intralevel low-k dielectrics. J Appl Phys, 2005, 98:084109 doi: 10.1063/1.2112171
[12]
Chen F, Bravo B, Chanda K, et al. A comprehensive study of low-k SiCOH TDDB phenomena and its reliability lifetime model development. Proceedings of International Reliability Physics Symposium, 2006:46
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    Haochun Qi, Xiaoling Zhang, Xuesong Xie, Li Zhao, Chengju Chen, Changzhi Lü. The expression correction of transistor current gain and its application in reliability assessment[J]. Journal of Semiconductors, 2014, 35(9): 094008. doi: 10.1088/1674-4926/35/9/094008
    H C Qi, X L Zhang, X S Xie, L Zhao, C J Chen, C Z Lü. The expression correction of transistor current gain and its application in reliability assessment[J]. J. Semicond., 2014, 35(9): 094008. doi:  10.1088/1674-4926/35/9/094008.
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    Received: 09 January 2014 Revised: 13 March 2014 Online: Published: 01 September 2014

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      Haochun Qi, Xiaoling Zhang, Xuesong Xie, Li Zhao, Chengju Chen, Changzhi Lü. The expression correction of transistor current gain and its application in reliability assessment[J]. Journal of Semiconductors, 2014, 35(9): 094008. doi: 10.1088/1674-4926/35/9/094008 ****H C Qi, X L Zhang, X S Xie, L Zhao, C J Chen, C Z Lü. The expression correction of transistor current gain and its application in reliability assessment[J]. J. Semicond., 2014, 35(9): 094008. doi:  10.1088/1674-4926/35/9/094008.
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      Haochun Qi, Xiaoling Zhang, Xuesong Xie, Li Zhao, Chengju Chen, Changzhi Lü. The expression correction of transistor current gain and its application in reliability assessment[J]. Journal of Semiconductors, 2014, 35(9): 094008. doi: 10.1088/1674-4926/35/9/094008 ****
      H C Qi, X L Zhang, X S Xie, L Zhao, C J Chen, C Z Lü. The expression correction of transistor current gain and its application in reliability assessment[J]. J. Semicond., 2014, 35(9): 094008. doi:  10.1088/1674-4926/35/9/094008.

      The expression correction of transistor current gain and its application in reliability assessment

      DOI: 10.1088/1674-4926/35/9/094008
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      • Corresponding author: Qi Haochun, Email:jetqi@sina.com
      • Received Date: 2014-01-09
      • Revised Date: 2014-03-13
      • Published Date: 2014-09-01

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