J. Semicond. > 2015, Volume 36 > Issue 9 > 094001
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SEMICONDUCTOR DEVICES

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

S. Intekhab Amin and R. K. Sarin

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 Corresponding author: intekhabamin@gmail.com

DOI: 10.1088/1674-4926/36/9/094001

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Abstract: The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L1) for a given gate length (L) are also studied and the optimum lengths L1 under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.

Key words: dual material double gate (DMDG), junctionless transistor, inversion mode transistor, gate misalignment, analog FOMs



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Fig. 1.  2D device structure of (a) DMDGJLT and (b) DMDGIMT. (c) Gate misalignment towards source side (MA_S). (d) Gate misalignment towards drain side (MA_D).

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Fig. 2.  Calibration of surface potential for SMDGJLT[12] and DMDGJLT[29] for $V_{\rm GS}=$ 0 V under different $V_{\rm DS}$.

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Fig. 3.  Simulated surface potential calibration against DMDGIMT data from[34] at $V_{\rm GS}=V_{\rm T}$ and $V_{\rm DS}$ $=$ 50 mV.

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Fig. 4.  (Color online) $I_{\rm D}$ and $g_{\rm m}$ as a function of gate voltage under gate misalignment condition at $V_{\rm DS}$ $=$ 1.0 V for (a) MA_S of DMDGJLT,(b) MA_D of DMDGJLT,(c) MA_S of DMDGIMT,(d) MA_D of DMDGIMT.

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Fig. 5.  (Color online) $g_{\rm ds}$ as a function of drain voltage under gate misalignment condition at $V_{\rm GS}$ $=$ 0.5 V for (a) MA_S of DMDGJLT,(b) MA_D of DMDGJLT,(c) MA_S of DMDGIMT,(d) MA_D of DMDGIMT.

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Fig. 6.  Transconductance ($g_{\rm m})$ as a function of gate misalignment where negative $x$-axis is for MA_S and positive $x$-axis for MA_D configuration with different length $L_1$ at $V_{\rm GS}$ $=$ 0.5 V and $V_{\rm DS}$ $=$ 1.0 V for (a) DMDGJLT and (b) DMDGIMT.

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Fig. 7.  Output conductance ($g_{\rm ds})$ as a function of gate misalignment where negative $x$-axis is for MA_S and positive $x$-axis for MA_D configuration with different length $L_{1}$ at $V_{\rm GS}$ $=$ 0.5 V and $V_{\rm DS}$ $=$ 1.0 V for (a) DMDGJLT and (b) DMDGIMT.

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Fig. 8.  Intrinsic gain ($A_{\rm VO})$ as a function of gate misalignment where negative $x$-axis is for MA_S and positive $x$-axis for MA_D configuration with different length $L_{1}$ at $V_{\rm GS}$ $=$ 0.5 V and $V_{\rm DS}$ $=$ 1.0 V for (a) DMDGJLT and (b) DMDGIMT.

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Fig. 9.  Cut-off frequency ($f_{\rm T})$ as a function of gate misalignment where negative $x$-axis is for MA_S and positive $x$-axis for MA_D configuration with different length $L_{1}$ at $V_{\rm GS}$ $=$ 0.5 V and $V_{\rm DS}$ $=$ 1.0 V for (a) DMDGJLT and (b) DMDGIMT.

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    Received: 01 November 2014 Revised: Online: Published: 01 September 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(9): 094001
      S. Intekhab Amin, R. K. Sarin. The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor[J]. Journal of Semiconductors, 2015, 36(9): 094001. doi: 10.1088/1674-4926/36/9/094001 ****S. I. Amin, R. K. Sarin. The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor[J]. J. Semicond., 2015, 36(9): 094001. doi:  10.1088/1674-4926/36/9/094001.
      Citation:
      S. Intekhab Amin, R. K. Sarin. The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor[J]. Journal of Semiconductors, 2015, 36(9): 094001. doi: 10.1088/1674-4926/36/9/094001 ****
      S. I. Amin, R. K. Sarin. The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor[J]. J. Semicond., 2015, 36(9): 094001. doi:  10.1088/1674-4926/36/9/094001.
      shu

      The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

      DOI: 10.1088/1674-4926/36/9/094001

      • Department of Electronics and Communication Engineering, Dr. B. R. Ambedkar National Institute of Technology Jalandhar, Punjab, 144011, India

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      • Corresponding author: intekhabamin@gmail.com
      • Received Date: 2014-11-01
      • Accepted Date: 2015-04-11
      • Published Date: 2015-01-25

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