1. Introduction
Phase-locked loops (PLLs) are one of the most important blocks in wireless radio frequency ( RF) transceivers,because they provide precise and high-speed clocks with low noise (jitter) at low power for transmit and receive data paths. The quadrature voltage controlled oscillator (QVCO) plays a very important role in the PLL circuit for the RF transceiver system based on low-IF or direct conversion architectures. Phase noise (PN),tuning range,driving capability,oscillation frequency,and power consumption are important features of QVCOs. There exists tradeoff among all these specifications. In modern multi-band multi-standard transceivers,to increase the tuning range without heavily affecting the PN performance is a major challenge. Recently,research on injection locking is implemented to improve the phase noise of the phase locked loop (PLL)[1, 2, 3]. Injection of a periodic signal into an oscillator can lead to interesting locking and pulling phenomena. Many authors have studied the behavior of injection locked oscillators: there are many papers and publications that have explained the specifications of injection locked QVCOs[4, 5, 6]. The injection locked oscillator (ILO) has been widely used for synchronizing,frequency multiplying and frequency dividing as well[7, 8, 9],because it has a relatively simple circuit and low phase noise.
The goal of this work is the analysis of phase noise in injection locked quadrature oscillators and the design of a low phase noise and wide band architecture accordingly. By using the superharmonic injection-locked techniques in two cross-coupled LC-tank VCOs,we can cancel the phase noise to a certain degree. By using a 5-bit switch capacitor array in addition to linearly varying MOS varactors,our design accomplishes a wide tuning frequency range. A new circuit has been implemented in the TSMC 0.18 μm CMOS technology,which operates in the 4.53--5.39 GHz band. The rest of the paper is organized as follows. In Section 2,the theory of the injection locked and QVCO is analyzed,based on the research of Adler's equation and Razavi's frequency shift theory. In Section 3 the proposed QVCO architecture and the design issues for the core,and LC tank is presented,the analysis of the quadrature topology with the superharmonic injection locked method,orthogonal oscillator phenomenon,phase noise,and wide band is given. In Section 4 the simulated and experimental results on a 0.18 μm model technology are given,and the comparison with the other papers is presented. Finally,Section 5 summarizes our work by presenting conclusions.
2. Design issue in injection lock QVCO
2.1 Injection lock
In general,an oscillator with a natural frequency ω0 can be injected with an external stimulus at a frequency that is harmonically related to ω0 ± Δω,where Δω is the locking bandwidth. Figure1(a) shows a simple injection-locked LC oscillator consisting of an ideal positive feedback amplifier,a tuned LC tank (L and Cvar) and a feedback path; the feedback path includes a summing point to allow injection of signals. Without an injecting signal,in the ideal condition,the LC oscillator runs at its free-running frequency,which is the resonance frequency
If a sinusoidal signal Iinj (ωinj ≠ ω0) is injected into the circuit,the tank current is a sum of the injected and transistor current,as shown in Figure1(b). If the amplitude and frequency of Iinj are chosen properly,the circuit indeed oscillates at ωinj rather than at ω0,the injection locking occurs,and the tank impedance contributes a nonzero phase shift ϕ ≠ 0.
In order for the oscillator loop gain to be equal to unity with zero phase shift,the sum of the current of the transistor and the injected currents must have the proper phase shift to compensate for the tank phase shift,since the loop gain has to have exactly a 2π phase shift. Hence,the ILO introduces a phase shift θ between the injected clock and the oscillator output signal,as seen in Figure1(b).
According to Adler and Razaver's research about injection locking,the relationship between θ and ϕ is given below[4, 5]:
the required frequency shift is:
and the lock range of fundamental (full-rate) injection is given by
According to Equation (4),the locking range of the proposed QVCO is wider as the injection signal power increases. In addition,the Q-factor and output power of the oscillator are in inverse proportion to the locking range.
The phase noise of oscillators can be reduced by injection locking to a low-noise source,as shown in Figure1(d). From a time-domain perspective,injection locking can lower the accumulation of jitter,namely phase noise characteristics,because the ``synchronizing'' effect of injection manifests itself as correction of the oscillator zero crossings in every period[5].
2.2 QVCO with injection lock
QVCOs with injection locking can be categorized by the coupling networks,the conventional QVCO is designed by using four coupling transistors either parallel to or in a series with the switch transistors[10, 11],to force the two VCOs oscillating in quadrature. They were P-QVCO (parallel QVCO) and S-QVCO (series QVCO),while the first and best known implementation is the P-QVCO proposed by Rofougaran et al.[10] whose coupling transistors (Mc) are in parallel with switch transistors (Ms) as shown in Figure2. The P-QVCO delivers four quadrature signals exhibiting low phase and amplitude errors; it has not been used extensively because of its poor phase noise performance although it is based on LC-tank VCOs. Many other QVCOs are realized by coupling the switching cross coupled transistors at the common source node via an integrated transformer or through a direct coupling circuit,or through the body of the transistor[12, 13, 14].
In all forementioned cases,a signal is injected from one VCO into the other at the fundamental frequency ω0 of operation,which may introduce unwanted parasitics,increase the power consumption and degrade the phase-noise. However,the quadrature VCO proposed here,has coupling oscillators which couple the signal at second harmonic frequency 2ω0 of two VCOs instead of the fundamental frequency ω0,which are usually called superharmonic coupled QVCOs. Superharmonic coupled QVCOs are preferred to traditional cross-coupled QVCOs for quadrature signal source design with reduced phase-noise and chip size[9].
3. Circuit design
The schematic of the proposed wide band superharmonic injection-locked QVCO circuit is shown in Figure3; it is composed of a cross-coupled VCO consisting of transistors Mn1,Mn2 and Mn3,Mn4,with the LC tank. The cross-coupled pair compensates for the tank loss to ensure start-up and sustains self-oscillation at ω0. The voltage Vctrl is used to tune the capacitance of varactors and the oscillator frequency continuously while the switched capacitor array (SCA) executes coarse tuning of frequency. Transistors Mn7,Mn8,Mn9,and Mn10 consist of two frequency-doubled differential pairs to double the resonant frequency as shown in Figure3(b). The input signal of the frequency doubler is the output signal of the LC resonator oscillating in resonant frequency ω0,when the differential signals are separately inputted into the gate of the transistor,the transistor pair converts the differential voltages into a time-varying current at the drain of the transistor with the double frequency of the input signal[15]. The doubled frequency will be injected into the cross-coupled pair in Vs1 and Vs2 to generate the quadrature signals Q+,Q−and I+,I−,the coupling network here locks the two VCOs through their second order harmonic component rather than through their fundamental component.
3.1 Principle of quadrature signal generation
The mechanism for quadrature signal generation of the proposed circuit is shown in Figure4 as a combination of functional block diagrams. The cross-coupled differential VCOs operate as a mixer for the signals injected at the common source nodes to the outputs with the local oscillation signal.
Assume that the unlocked differential output signal is:
The second harmonic injected currents are as follows:
Suppose the drive signal is not a pure sine wave,but rather a square wave. Expressions of the drive signal are obtained by Fourier transformation:
Using Kirchhoff's current law at nodes I+ and I− and simplifying the equation yields the following result:
After the mixer,the output signal is[16]:
Due to the frequency selected effect of the LC load,most of the high frequency components will be filtered,and the higher order harmonics will be neglected.
The tail current which is being switched by the NMOS cross-coupled differential pair is composed of the bias current Idc and the injection current Iinj at 2ω from the other LC core:
and a differential tank oscillation amplitude given by
where m=Iinj/Idc,representing the coupling strength of QVCO. When the I side and Q side VCOs are perfectly matched,gives[17] ϕI−2θI=ϕQ−2θQ,leading to the following phase relationship:
where ϕI,ϕQ is the phase difference between the common mode signals at Vs1 and Vs2,θI and θQ is the phase difference between the output waveforms VI and VQ. Then ultimately,if the second order harmonic components of the common-mode signals are forced to 180∘ out of phase,VI and VQ will yield a quadrature phase relationship.
3.2 Wide band
Motivated by the need to cover multiband or wideband standards with robust operation,we need to focus on widening the tuning range of QVCOs. As seen from Figure3,in the proposed circuit,the LC tank circuit consists of inductors,accumulation mode MOS (AMOS) varactors,and a switched capacitor array (SCA). Frequency calibration consists of two steps of fine tuning and coarse tuning to widen the operating frequency range. In LC-oscillators,varactors are used for continuous frequency tuning. Since p--n junction varactors and inversion mode MOS varactors have limited tuning range and non-linear behavior[18],to achieve a wider tuning range and linearity in integrated VCOs,accumulation-mode MOS (AMOS) varactors are commonly preferred. Two pairs of varactors,C1,C2 and C3,C4 are AMOS varactors,which are used to vary the capacitance whose value is dependent on the control voltage (Vctrl).
To improve the linearity and reduce the flicker noise up-conversion,the 5-bit binary weighted MOS capacitor SCA is employed for coarse frequency tuning which is best suited for low cost applications as it occupies a smaller area than a poly capacitor SCA.
In the proposed circuit,the output frequency is:
where CV is the varactor capacitance,which is controlled by the voltage of Vctrl,and CB is the capacitance given by the switch capacitor. In binary-weighted capacitive array,CB is linearly proportional to the capacitor bank code n as follows:
where C is the unit capacitance of the bank,A is a constant,and N represents the maximum value of the code n,here it is 5.
A schematic of the MOS capacitor SCA is shown in Figure5. The 5-bit SCA is constructed with five switched-capacitor branches in parallel,each branch consists of a unit capacitor in series with an MOS transistor as a digital switch. By digitally controlling the gates of the MOS switches,the total capacitance can be controlled,and the oscillation frequency can be tuned. The unit capacitors in an SCA can be designed to be of the same value to be binary-weighted[19, 20].
Figure6 shows the physical layout of the multi-band VCO. The oscillator is tunable between 3.53 (B0:B4 in 11111) and 5.39 GHz (B0:B4 in 00000) achieving a tuning range of 41.7% with a tuning voltage of 0 to 1.8 V,as shown in Figure7.
3.3 Analysis of the phase noise
Phase noise is the most important performance indicator of the quadrature oscillator,which can cause several types of signal degradations that are very difficult to quantify analytically. Generally,the noise sources of the oscillator include the parasitic resistance noise from the LC tank,the channel thermal noise,flicker noise (1/f noise) in the transistor at low frequencies and the gate noise of the transistor.
A lot of models have been proposed to analyzed the phase noise of the oscillator,the typical model is given by Leeson as follows:
where k is the Boltzmann constant,T is the absolute temperature,Q is the loaded quality factor of the tank,F is the experience factor of adjusting the phase noise curve,Psig is the signal power,fm is the diverge frequency,and f1/f is the frequency of the flicking noise of the active device. As shown in Equation (13) the direct way to reduce the phase noise is to increase the Psig ∝ V2peak,another efficient way to reduce the phase noise is to get a tank with high Q.
In the oscillating frequency fosc,the quality factor of the LC tank is defined as:
Combining Equations (14) and (13),yields:
Obviously,the power spectral density of the noise is frequency dependent because of the filtering effection of the tank,falling as the inverse-square of the offset frequency. The phase noise of an oscillator is relevant to the equivalent resistance of the tank,despite the inevitable equivalent resistance,the phase noise can also be optimized by other means.
The main flicker noise is from the switching differential cross-coupled transistor pair,it generates the fundamental frequency carrying with flicker noise which down-converted to fundamental frequency and the noise is added to the phase noise sideband. In conventional QVCO,the common mode node of a cross-coupled pair works at a fixed voltage,the low-frequency device noise of the tail can be up-converted to the phase noise of the oscillator,while in the proposed circuit,a dynamically switched current source is achieved by superharmonic injection feedback paths,which provide a dynamic switching current,instead of DC bias switching,to reduce 1/f noise. The low-frequency flicker noise is related to the long occupation time constants of the traps close to the SiO2 interface of the MOSFET channel. As a switched transistor will force a trap to release its captured electron so that the transistor becomes memory-less,the flicker noise will be reduced[21].
On the other hand,in the quadrature output state,the tail current at the double frequency of the oscillator frequency ω0 reaches its minimum value during zero-crossing of the tank differential voltage and the VCO core is biased at the onset of the voltage limited regime. Therefore,the phase noise in mutually synchronized oscillators is lower than that of a single oscillator if the coupling network is reciprocal. As shown in Figure8 of the four simulated quadrature output waveforms,it shows that the drain--source and gate--source voltages of cross-coupled pair transistors periodically reach a value close to zero. As a result,the noise of transistors 1/f noise is reduced[17].
4. Simulation and measurement results
The proposed wideband injection lock QVCO was designed and fabricated using the TSMC 0.18 μm mixed-signal/RF CMOS 1P6M technology. Figure10 shows the chip photograph of the fabricated QVCO,the chip size is 1.19 × 1.09 mm2 with pad included. The output spectrum and phase noise of the QVCO are measured using an Agilent E4440 spectrum analyzer. The total power consumption is 12 mW with a 1.8 V supply voltage.
As illustrated in Figure9(a),the simulation results based on SpectreRF indicate that this quadrature VCO achieves a phase noise of 132.1 dBc/Hz at 1 MHz offset,over the frequency range from 3.53 GHz to 123.9 dBc/Hz at 5.39 GHz,while the measured result of phase noise is 127.98 dBc/Hz at 1 MHz offset at 4.85 GHz as shown in Figures 9(b) and 9(c). A common figure of merit (FoM) was defined to evaluate the overall performance:
where ω0 is the frequency of oscillation,Δω is the offset frequency ,L{Δω} is the phase noise at Δω,and PD is the power dissipated in the oscillator core in milliwatts. For the proposed quadrature VCO,a FoM of 181.7 dBc/Hz is achieved at 4.85 GHz at a VDD of 1.8,consuming 12 mW of power. Table1 presents a comparison between this work and other publications.
5. Conclusion
An integrated 3.53--5.39 GHz multi-band,superharmonic injection lock low phase noise LC QVCO is designed,and fabricated in a 0.18 μm TSMC CMOS technology process. The proposed QVCO introduces a coupling network that operates as a frequency doubler locking the two VCOs through their second order harmonic component,and it can be tuned by using a 5-bit switching capacitor array and linearly varying AMOS varactors. The measured phase noise of the design circuit is around 127.98 dBc/Hz at 1 MHz offset frequency over the tuning range at 12 mW power consumption. Additionally,the figure of merit (FOM) that includes all important parameters such as phase noise,power consumption and division of operating frequency to offset frequency is 181.7 dBc/Hz.