1. Introduction

Time delay integration (TDI) is a technology to improve the signal to noise ratio (SNR) by multiple sampling and signals accumulating,and it is widely used in applications where a line-scan system is required for high quality and low noise imaging even under low illumination conditions and at a high scanning speed^{[1, 2]}. Since charge-coupled devices (CCDs) can accumulate the signal without noise,TDI is easy to realize by 2-D CCDs^[3]. However,CCDs demand a high voltage supply,and can hardly integrate with the pixel signal processing circuit.

On the other hand,TDI CMOS image sensors (CIS) are gradually studied because of the development of CMOS in noise and dark current,etc.^[4]. However,it is still the key for TDI CIS to design an accumulator with low-noise accumulation. Several reports on TDI CIS have been published recently. According to the exposure mode of pixels,TDI CIS can be divided into global shutter TDI CIS and rolling shutter TDI CIS. A global shutter TDI CIS is not the first option in TDI CIS,because the CDS operation cannot be adopted unless the transistors in pixel are more than five,which will result in a poor fill-factor and large pixel area. When the global shutter method is adopted,to get the high line readout speed,each TDI stage requires an individual amplifier and accumulation capacitors,which lead to the area increases,thus resulting in an increase in the price^{[5, 6]}. When amplifiers and capacitors are integrated to the pixel,the pixel fill-factor will decrease seriously^[7]. On the other hand,the CDS operation can be adopted in the rolling shutter TDI CIS,the column-level sharing amplifier can reduce the area and power consumption^[8].

A 128-stage TDI CIS is designed^[9],which is based on the rolling shutter structure^[8]. It is shown that improved SNR for rolling shutter structure TDI CIS is limited by not only the noiseless accumulation but also the impact of layout parasitics of the accumulator^[9]. Although the decoupling capacitor is added in the accumulator to decrease the impact of parasitics,the improved SNR reaches only 16.6 dB @ 128-stage,while it is 21.07 dB @ 128-stage in an ideal case^[9]. Therefore,it is necessary to resolve the impact of parasitics completely in high-stage accumulators. To resolve the impact of parasitics,the decoupling switch and positive feedback capacitance compensation were employed in a previous design,but it limits the speed of the circuit. In this paper,a new accumulator structure based on the one presented^[8] is proposed. The charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with the decoupling switch. Then an additional calibration circuit is used to restrain the mismatch and process,voltage and temperature (PVT) variations. The result of post layout simulation indicates that the proposed accumulator is suitable for the design of high-stage TDI CIS.

The remainder of this paper is organized as follows. In Section 2,the principle of the proposed accumulator^[8] and the impact of parasitic capacitance are introduced. In Section 3,an optimized accumulator is proposed. In Section 4,the post layout simulation results of the proposed accumulator are shown. A brief conclusion is drawn in Section 5.

2. The limitations of the accumulator with the increase in stages

2.1 The principle of analog accumulator

The analog accumulator in the CMOS TDI image sensor^[8] is shown in Figure 1,in which there are $N+1$ integrators,an operational amplifier (OPA) with the offset considered and the sample capacitor $C_{\rm S}$. Since the offset of the OPA due to the process variation is a very low-frequency noise,it can be modeled as a time-invariant voltage $V_{\rm os}$ as shown in Figure 1^[10]. The $N+1$ integrators can realize $N$-stage signal accumulation in the $N$-stage CMOS TDI image sensor with a temporal oversampling rate of (N+1)/N^{[8, 11]}. The common-mode noise including clock coupling,ground noise and charge injection will be restrained by the fully-differential topology. The timing diagram of the accumulator is shown in Figure 2,which is based on two-phase non-overlapping technology to avoid the signal dependent charge injections^[12].

Pixel noise and the offset of the OPA will be eliminated by the multi-stage switch-capacitor (SC) integrator. The first integrator of the accumulator is considered for an example to describe how the accumulator works as follows. The reset switch is closed by Reset1 and Reset$1'$ to clear the charges stored in $C_{\rm H1}$ when the integrator is in the first sampling phase. Clk1 is closed to sample the pixel resetting signal $V_{\rm rst}$ and the OPA's input-referred offset $V_{\rm os}$ will be stored in the capacitor $C_{\rm S}$ at the same time,as shown in Figure 3(a). In this phase,the output of the OPA is the output common mode voltage $V_{\rm com,\,out}$ and the bottoms of the two holding capacitors have the same voltage $V_{\rm X}$. Then the integrator is in the integration phase when clk2 and I1 is closed to transfer the charges ($V_{\rm rst}-V_{\rm sig})C_{\rm S}$ from $C_{\rm S}$ to $C_{\rm H1}$ as shown in Figure 3(b). In this phase,the input common-mode voltage of the OPA is expressed as $V_{\rm com,\,in}$. Hence,the relation between the input and output of the first integrator can be expressed as:

$\label{eq1} \begin{array}{l} \left. {\begin{array}{l} (V_{\rm rst} -V_{\rm com,\,out} -V_{\rm os} )C_{\rm S} +(V_{\rm x} -V_{\rm com,\,out} -V_{\rm os})C_{\rm H} = \\[3mm] \quad (V_{\rm sig} -V_{\rm com,\,in} -V_{\rm os} )C_{\rm S} +(V_{\rm out-} -V_{\rm com,\,in} -V_{\rm os})C_{\rm H} \\[3mm] (V_{\rm ref} -V_{\rm com,\,out} )C_{\rm S} +(V_{\rm x} -V_{\rm com,\,out} )C_{\rm H} = \\[3mm] \qquad\qquad\qquad(V_{\rm ref} -V_{\rm com,\,in} )C_{\rm S} +(V_{\rm out+} -V_{\rm com,\,in} )C_{\rm H} \\[3mm] \end{array}} \right\} \\[15mm] \Rightarrow V_{\rm out-} -V_{\rm out+} =\dfrac{C_{\rm S} }{C_{\rm H} }(V_{\rm rst} -V_{\rm sig} ) \Rightarrow \upDelta V_{\rm out} (1) =\dfrac{C_{\rm S} }{C_{\rm H} }\upDelta V_{\rm in}\\[4mm] \upDelta V_{\rm out} (1)=V_{\rm out-} -V_{\rm out+},\quad \upDelta V_{\rm in} =V_{\rm rst} -V_{\rm sig}. \end{array}$

(1)

After the $N$-th integration,the output of the first integrator can be expressed as:

$\label{eq2} \upDelta V_{\rm out} [N]=\upDelta V_{\rm out} [N-1]+\frac{C_{\rm S} }{C_{\rm H} }\upDelta V_{\rm in} .$

(2)

Because of the same holding capacitor in every integrator,Equation (2) is suitable for any integrator without considering mismatch. So the gain for any integrator in the accumulation can be got from Equation (2) as:

$\label{eq3} g[x]=\frac{\upDelta V_{\rm out} [x]-\upDelta V_{\rm out} [x-1]}{\upDelta V_{\rm in} }=\frac{C_{\rm S} }{C_{\rm H} }.$

(3)

Based on the TDI principle,SNR$_{\rm add}$,which means the improved SNR,can be expressed as:

$\label{eq4} {\rm SNR}_{\rm add} =20\lg \frac{\sum\limits_{i=1}^N {g[i]} }{\sqrt {\sum\limits_{i=1}^N {g^2[i]}}} =10\lg N.$

(4)

It can be seen from Equation (2) that the output of the accumulator does not include the pixel noise and offset of the OPA. At the same time,an ideal improved SNR is realized in Equation (4) without considering the impact of parasitics and the noise of the accumulator.

The thermal noise has set fundamental limits in the design of the analog circuits^[13]. As analyzed in our previous work^[8],with the assumption,$C_{\rm S}=C_{\rm H}=C$,the total thermal noise contributed by the accumulator can be expressed as:

$\label{eq5} \overline {V_{\rm Ntot} } =\sqrt {\frac{6N}{3} \frac{kT}{C}} ,$

(5)

where $k$ is the Boltzmann constant,and $T$ is the absolute temperature. Therefore,the improved SNR of the accumulator will be smaller than the ideal ones due to the thermal noise. The layout parasitics of the accumulator will lower the effective number of accumulator stages; according to Equation (4),the improved SNR is also reduced^[9]. The emphasis of this paper is to reduce the parasitics,and to improve the SNR,so the effect of noise is ignored in the next analysis.

2.2 The impact of parasitics

The parasitics of the metal wires and vias in the layout design of the accumulator is the basic source which decreases the precision of the accumulator. The main parasitics include the internal parasitic capacitor of the holding capacitor,the parasitic capacitor of the input and output bus,and the parasitic capacitor of the OPA and sampling capacitance. Around the holding capacitor $C_{\rm H}$,there are more MOS switches,and the metal wire is more crowded relative to the sampling capacitor $C_{\rm s}$. For the $N$-stage accumulator,the holding capacitor $C_{\rm H}$ is located between the input and output bus. The parasitic capacitor of the holding capacitor $C_{\rm H}$ is the main factor that influences the performance of the accumulator. The parasitic capacitor of the sampling capacitor $C_{\rm s}$ only affects the gain of the OPA and has little influence on the effective number of accumulator stages. Compared to the parasitic capacitor of the $C_{\rm H}$,the impact of the parasitic capacitor of $C_{\rm s}$ plays a negligible or minor role. We can restrain the impact of $C_{\rm s}$ by the symmetrical layout. Next we will analyse the parasitics of the $C_{\rm H}$ and long bus in detail.

Because of the parasitics in the layout of the accumulator,there is a parasitic capacitor connected between the top or bottom plate of the holding capacitor in each integrator of the accumulator and the input or output of the OPA. The parasitic capacitors in the $i$-th integrator of the accumulator are shown in Figure 4. In Figure 4,the idle integrator can be equivalent to $C_{\rm pi}$ by Y-delta transformation^[14].

$\label{eq6} \begin{cases} C_{\rm p12i} =(C_{\rm pbbi} \times C_{\rm ptti} )/(C_{\rm pbbi} +C_{\rm ptti} +C_{\rm H})\approx 0,\\[2mm] C_{\rm p23i} =(C_{\rm ptti} \times C_{\rm H} )/(C_{\rm pbbi} +C_{\rm ptti} +C_{\rm H})\approx C_{\rm ptti},\\[2mm] C_{\rm p13i} =(C_{\rm pbbi} \times C_{\rm H} )/(C_{\rm pbbi} +C_{\rm ptti} +C_{\rm H} )\approx C_{\rm pbbi}. \\ \end{cases}$

(2)

The parasitic capacitors $C_{\rm p12i}$,$C_{\rm p23i}$ and $C_{\rm p13i}$ expressed as Equation (6) are the equivalent capacitors of $C_{\rm H}$,$C_{\rm pbbi}$ and $C_{\rm ptti}$. Therefore,the $C_{\rm pi}$ is:

$\begin{split} \label{eq7} C_{\rm pi} {}& =\frac{(C_{\rm p13i} +C_{\rm ptbi} ) (C_{\rm p23i} +C_{\rm pbti} )}{C_{\rm p13i} +C_{\rm ptbi} +C_{\rm p12i} +C_{\rm pbti} }+C_{\rm p12i} \\[2mm]& \approx \frac{(C_{\rm pbbi} +C_{\rm ptbi} )(C_{\rm ptti} +C_{\rm pbti} )}{C_{\rm pbbi} +C_{\rm ptbi} +C_{\rm ptti} +C_{\rm pbti} }. \end{split}$

(7)

Therefore,the $i$-th idle integrator is equivalent to a parasitic capacitor $C_{\rm pi}$. For analyzing the impact of parasitics,the models of the accumulator,where the 1st integrator is in the sampling phase or in the integration phase,are shown in Figures 5(a) and 5(b). In the sampling phase,the input and output of the OPA are reset by clk',so the charge in $C_{\rm pi}$ is cleared. In the integration phase,the lower plate of $C_{\rm pi}$ will get the charge from the sample capacitor,which decreases the gain of the accumulation. Furthermore,the higher the voltage on the top plate of $C_{\rm H1}$ is,the more charges the bottom plate of $C_{\rm pi}$ obtains.

All the parasitic capacitances of the idle integrator are the same in the case of ignoring mismatch. Thus the total parasitic capacitor $C_{\rm ptotal}$ can be expressed as:

$\label{eq8} C_{\rm ptotal} =N C_{\rm pi} .$

(8)

Considering the parasitics analyzed above,the charge transfer relationship in Equation (2) changes to:

$\begin{array}{l} \Delta {V_{{\rm{in}}}} \times {C_{\rm{S}}} + \Delta {V_{{\rm{out}}}}[N - 1] \times {C_{\rm{H}}} = \Delta {V_{{\rm{out}}}}[N] \times ({C_{\rm{H}}} + {C_{{\rm{ptotal}}}})\\ \Rightarrow \Delta {V_{{\rm{out}}}}[N] = \frac{{{C_{\rm{S}}}}}{{{C_{\rm{H}}} + {C_{{\rm{ptotal}}}}}}\Delta {V_{{\rm{in}}}}\\ {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} {\kern 1pt} + \frac{{{C_{\rm{H}}}}}{{{C_{\rm{H}}} + {C_{{\rm{ptotal}}}}}}\Delta {V_{{\rm{out}}}}[N - 1]. \end{array}$

(9)

After the first integration of the first integrator,the differential output is:

$\label{eq10} \upDelta V_{\rm out} [1]=\frac{C_{\rm S} }{C_{\rm ptotal} +C_{\rm H} }\upDelta V_{\rm in} .$

(10)

According to Equations (9) and (10),a common equation about the $x$-th integration of the first integrator can be expressed as:

$\label{eq11} V_{\rm out} [x]=\alpha V_{\rm in} \sum\limits_{i=1}^x {K^{i-1}} ,$

(11)

where

$\label{eq12} \alpha =\frac{C_{\rm S} }{C_{\rm H} +C_{\rm ptotal} },\quad K=\frac{C_{\rm H} }{C_{\rm H} +C_{\rm ptotal} }.$

(12)

So the gain for any integrator in the accumulation can be expressed as:

$\label{eq13} g[x]=\frac{\upDelta V_{\rm out} [x]-\upDelta V_{\rm out} [x-1]}{\upDelta V_{\rm in} }\approx \alpha K^{x-1}.$

(13)

Based on the TDI principle and Equation (13),the improved SNR with the parasitics considered can be expressed as:

$\label{eq14} {\rm SNR}_{\rm add} =20\lg \frac{\sum\limits_{i=1}^N {g[i]} }{\sqrt {\sum\limits_{i=1}^N {g^2[i]} } } =10\lg\left( \frac{1+K}{1-K} \frac{1-K^N}{1+K^N}\right).$

(14)

When the parameter $K$ is equal to 1,Equation (14) transforms to Equation (4). However,$K$ is less than 1 because of the impact of parasitic capacitor $C_{\rm ptotal}$. Furthermore,while $C_{\rm ptotal}$ increases with the accumulation stage,$K$ gets worse. In order to show the parasitic phenomenon in the accumulator more directly,one integrator of the accumulator is designed and optimized with a 0.18 $\mu$m 1P4M CMOS technology,and the layout is shown in Figure 6.

The parasitic capacitor $C_{\rm pi}$ in the layout is extracted and its capacitance is 0.449 fF,when the capacitance of the holding capacitor $C_{\rm H}$ is 980 fF. Based on Equations (8),(12) and (14),the curve of the improved SNR versus the designed stage number of the accumulator can be derived,which is shown in Figure 7. From Figure 7,it can be seen that the parasitic phenomenon can lower the improved SNR dramatically,especially when the designed stage number is larger than 50,because the effective number of the accumulator stage becomes small significantly.

3. The optimized accumulator

3.1 Compensate the impact of parasitism

In order to make the proposed structure suitable for high-stage TDI CIS application,it is necessary to eliminate the impact of parasitics. In previous work^[15],a small decoupling switch controlled by IDx is employed to decrease the impact of the parasitics of the integrator as shown in Figure 8. The timing diagram of the accumulator is shown in Figures 9(a) and 9(b).

Because of the decoupling switch,an alternating current (AC) ground is added to the bottom plate of the integrator capacitor in the equivalent circuit which is shown in Figure 10. When the decoupling switch is closed,the parasitic capacitors,$C_{\rm ptbi}$ and $C_{\rm pbti}$,etc.,which make great contributions to $C_{\rm pi}$,will be equivalent to the loads of the input or the output of the OPA thanks to the AC ground. So the equivalent parasitic capacitor $C_{\rm pi}$ is changed to:

$\label{eq15} C_{\rm pi} =C_{\rm p12i} =\frac{C_{\rm ptbi} C_{\rm pbti} }{C_{\rm ptbi} +C_{\rm pbti} +C_{\rm Hi} }\approx 0.$

(15)

However,the impacts which come from the parasitic capacitance of the sample switch,clk1',the non-ideal OPA and the parasitics of the bus cannot be eliminated in a simple way. Therefore,it is necessary to compensate the parasitics which cannot be eliminated for obtaining an accumulator with ideal performance.

In the previous design,the bottom plate sampling technology is used to eliminate the effect of channel charge injection. In this paper,the top plate sampling is applied for utilizing the charge injection of the top plate switch to compensate the parasitic capacitance. The schematic is shown in Figure 11. The two switching sequences on both sides of the holding capacitor are exchanged to realize the top plate sampling.

Channel charge injection is analyzed that the MOS transistors with low $W/L$ and the fast clock edge lead to equally distributing the charge across the switch^[17]. In this situation,the charge injection of the top plate CMOS switch,$\upDelta Q$,can be expressed as:

$\label{eq16} \begin{array}{l} \left. {\begin{array}{l} \left. {\begin{array}{l} Q_{\rm N+} =\dfrac{1}{2}(WL)_{\rm N} C_{\rm ox} \left( {{\rm VDD}-V_{\rm out+} } \right) \\[2mm] Q_{\rm N-} =\dfrac{1}{2}(WL)_{\rm N} C_{\rm ox} \left( {{\rm VDD}-V_{\rm out-} } \right) \\[2mm] \end{array}} \right\} \\ \Rightarrow \upDelta Q_{\rm N} =\dfrac{1}{2}(WL)_{\rm N} C_{\rm ox} \upDelta V_{\rm out} \\[2mm] \left. {\begin{array}{l} Q_{\rm P+} =\dfrac{1}{2}(WL)_{\rm P} C_{\rm ox} \left( {{\rm GND}-V_{\rm out+} } \right) \\[2mm] Q_{\rm P-} =\dfrac{1}{2}(WL)_{\rm P} C_{\rm ox} \left( {{\rm GND}-V_{\rm out-} } \right) \\[2mm] \end{array}} \right\} \\ \Rightarrow \upDelta Q_{\rm P} =\dfrac{1}{2}(WL)_{\rm P} C_{\rm ox} \upDelta V_{\rm out} \\[2mm] \end{array}} \right\} \\[2mm] \Rightarrow \upDelta Q=\upDelta Q_{\rm N} +\upDelta Q_{\rm P} =\dfrac{1}{2}\upDelta V_{\rm out} C_{\rm ox} [\left( {WL} \right)_{\rm N} +\left( {WL} \right)_{\rm P}],\\ \end{array}$

(16)

where $Q_{\rm N+}$ and $Q_{\rm N-}$ are the injection charge which come from the NMOS transistor in the top plate switch,and $Q_{\rm P+}$ and $Q_{\rm P-}$ are the injection charge which come from the PMOS transistor in the top plate switch. In case of $C_{\rm H}=C_{\rm S}$,$\upDelta Q$ will be equally distributed to $C_{\rm H}$ and $C_{\rm S}$. Thus,at the end of the integration phase,the change of the differential voltage in $C_{\rm H}$ can be expressed as:

$\label{eq17} \begin{split} {}& \upDelta V_{\rm out}^{'} =\upDelta V_{\rm out} +\frac{\frac{1}{2}\upDelta Q}{C_{\rm H} }\Rightarrow \\[1mm]& \frac{\upDelta V_{\rm out}^{'} }{\upDelta V_{\rm out} }=1+\frac{\frac{1}{4}C_{\rm ox} \left[{\left( {WL} \right)_{\rm N} +\left( {WL} \right)_{\rm P} } \right]}{C_{\rm H} }=\frac{C_{\rm H} +C_{\rm S\_eq} }{C_{\rm H}}, \\[1mm]& C_{\rm S\_eq} =\frac{1}{4}C_{\rm ox} \left[{\left( {WL} \right)_{\rm N} +\left( {WL} \right)_{\rm P} } \right]. \\ \end{split}$

(17)

Thus the parameter $K$ should be replaced by $K'$ as:

$\label{eq18} K^{'}=\frac{C_{\rm H} }{C_{\rm H} +C_{\rm ptotal} } \frac{C_{\rm H} +C_{\rm S_{eq} } }{C_{\rm H} }=\frac{C_{\rm H} +C_{\rm S_{eq} } }{C_{\rm H} +C_{\rm ptotal} }.$

(18)

It can be seen in Equation (18) that the unique $WL$ in MOS transistors of the top plate switch can realize $K'$ equaling to 1 when the top plate sampling is applied.

However,because of the threshold voltage of MOS transistors,the MOS transistors will be into the saturation region when the OPA has a large output. If the threshold voltages of NMOS and PMOS are $V_{\rm thN}$ and $V_{\rm thP}$,respectively,Equation (16) should be changed to:

$\label{eq19} \begin{array}{l} \left. {\begin{array}{l} Q_{\rm N+} =0, \quad V_{\rm out+} >V_{\rm thN} \\[4mm] Q_{\rm N-} =\dfrac{1}{2}(WL)_{\rm N} C_{\rm ox} \left( {\text{VDD}-V_{\rm out-} } \right) \\[4mm] Q_{\rm P+} =\dfrac{1}{2}(WL)_{\rm P} C_{\rm ox} \left( {\text{GND}-V_{\rm out+} } \right) \\[4mm] Q_{\rm P-} =0, \quad -V_{\rm out-} >V_{\rm thP} \\[4mm] \end{array}} \right\} \Rightarrow \\ \upDelta Q=\upDelta Q_{\rm N} +\upDelta Q_{\rm P} =\dfrac{1}{2}\upDelta V_{\rm out} C_{\rm ox} \left[{\left( {WL} \right)_{\rm N} +\left( {WL} \right)_{\rm P} } \right] \\[4mm] -\dfrac{1}{2}C_{\rm ox} \left[{(WL)_{\rm N} \left( {\text{VDD}-V_{\rm out+} } \right)+(WL)_{\rm P} \left( {\text{GND}-V_{\rm out-} } \right)} \right]. \\ \end{array}$

(19)

A simulation result about the increased voltage of the integrating capacitor in the top plate sampling versus the output voltage in the integrator is shown in Figure 12,which shows that a CMOS switch is not suitable as a linear compensation in the accumulator because of its nonlinear characteristics.

The layout about the bootstrapped switch is shown in Figure 15,where the area of the integrator does not increase when the bootstrapped switch is added because of the column-sharing charge pump.

The effect of the threshold voltage can be ignored in a bootstrapped switch. It should be noticed that the capacitance in the bootstrapped switch will occupy too much area if the bootstrapped switch is used in every integrator. Thus an implementation suitable for the TDI accumulator is shown in Figures 13 and 14,and the charge pump in Figure 14 is shared among the whole chip when the array is put into implementation. In Figure 13(a),when the $i$-th integrator is in the integration phase,four interaction MOS transistors are used to provide the controlled clock which reach up to bootstrapped voltage,$V_{\rm b}$. When the $i$-th integrator is not in the integration phase,the controlled clock will close the current path from $V_{\rm b}$ voltage to ground completely,as shown in Figure 13(b) ,which will not affect the operation of the other integrators. As shown in Figure 14,$V_{\rm b}$ is generated from a charge pump controlled by generating two-phase non-overlapping clocks,where $C_{\rm B}$ is a small capacitor which is used to preserve the bulk potential when switching^[16].

A simulation result about the change before and after closing the bootstrapped switch versus the output voltage in the integrator is shown in Figure 16. The linearity of the curve can be defined by the following:

$\label{eq20} {\rm Linearity}=\left( {1-\frac{\upDelta V_{\rm max } }{V_{\rm max } }} \right)\times 100\% ,$

(20)

where $V_{\rm max}$ is the accumulator's full scale output and $\upDelta V_{\rm max}$ is the maximum difference between the simulation and fitted transmission curves. So the linearity of the proposed bootstrapped switch is over 99.99%.

3.2 The adjustment for mismatch and PVT variation

In fact,the extracted parasitics are unreliable because of the process variation and mismatch. Thus a certain $WL$ of the bootstrapped switch cannot guarantee realizing an ideal accumulator. The higher the stages of the accumulator are,the closer to 1 the parameter $K'$ must be. For 1% deviation in SNR,the variation of $K'$ cannot exceed 0.5‰. However,it is impossible to regulate the $WL$ of the MOS transistors in a chip.

A correction technology for the uncertain parasitics is used in this paper. Here over-compensation in the bootstrapped switch,meaning a larger $WL$ of the bootstrapped switch than the theoretical value,is applied. At the same time,a correction circuit for surplus compensation is designed as shown in Figure 17,in which four capacitors that increase double are added between the input and the output of the OPA; whether they are involved in the accumulator is easily decided by the digital codes from $B_{1}$ to $B_{4}$,which come from a 4-bit counter triggered by Cal.Bit. So the parameter $K'$ is changed to $K''$:

$\label{eq21} K^{''}=\frac{C_{\rm H} +C_{\rm s\_eq} }{C_{\rm H} +C_{\rm total}^{'} +C_{\rm add} },$

(21)

where $C_{\rm add}$ is the capacitor enabled in the calibration circuit. Further,it can be deduced that for a $C_{\rm add}$ variation,the change in $K''$ can be expressed as:

$\begin{split} \label{eq22} \Rightarrow \frac{\upDelta K^{''}}{K^{''}}{} &= \frac{\partial K}{\partial C_{\rm add} }\frac{\upDelta C_{\rm add} }{K^{'}}=-\frac{\left( {C_{\rm H} +C_{\rm s\_eq} } \right)\upDelta C_{\rm add} }{\left( {C_{\rm H} +C_{\rm ptotal}^{'} +C_{\rm add} } \right)^2K^{''}} \\ & \approx -\frac{\upDelta C_{\rm add} }{C_{\rm H}}. \end{split}$

(22)

When $\upDelta C_{\rm add}$ $=$ 1 fF,the change in $K$ can be controlled in less than 0.1%,which can meet the requirements for an 800-stages accumulator with SNR declining up to 1%. On the other hand,the correction circuit can work when the parasitic capacitance extracted has 1% error compared to an actual situation. The smaller $\upDelta C_{\rm add}$ is designed,the more precise $K''$ can be achieved. While the more capacitors are added,the better parasitic variation can be restrained. The layout coming from Figure 17 is shown in Figure 18,where the capacitors in the calibration circuit are realized through the parasitics between metals for decreasing the mismatch.

4. Results

A 128-stage optimized accumulator suitable for TDI CIS is designed based on 0.18-$\mu$m one-poly four-metal 3.3 V CMOS technology. The capacitors used in the proposed accumulator are all metal-insulator-metal (MIM) capacitors with unit-area capacitance of 2 fF/$\mu$m$^{2}$,and the size of one accumulator channel is 0.03 $\times$ 11.25 mm$^{2}$ (each stage's size is 30 $\times$ 80 $\mu$m$^{2})$. The post layout simulations about the proposed accumulator are demonstrated as follows.

The curves of the output of the accumulator versus the times of the accumulation are shown in Figure 19,where the results of a traditional accumulator and the optimized accumulator are both given as a comparison. The improved SNR which is based on Equation (14) is 21.0670 dB for the proposed accumulator,20.8404 dB for the accumulator with the decoupling switch and 17.8349 dB for the traditional accumulator,while the ideal value is 21.0721 dB. The effective times of accumulation,$N_{\rm eff}$,can be expressed as:

$\label{eq23} {\rm SNR}_{\rm add} =20\lg _{10} \sqrt[2]{N_{\rm eff} }\Rightarrow N_{\rm eff} =10^{\frac{{\rm SNR}_{\rm add} }{10}}.$

(23)

So the effective times of accumulation proposed is in 127.85 stages.

To evaluate the accumulator's linearity,its outputs are simulated when the inputs are increasing linearly,the result and the linear fitting curve are shown in Figure 20. The linearity of the accumulator can be defined by Equation (20),where $\upDelta V_{\rm max}$ is the maximum difference between the simulated and fitted transmission curves. So the linearity of the accumulator is 99.62%,which is based on the result in Figure 20.

The calibration circuit for the mismatch and process variations is verified in this paper. The curves of the outputs of accumulators versus the times of the accumulation for different calibration codes are shown in Figure 21. Due to the restraint of the OPA's maximum output voltage,the voltage gets into saturation when the time of accumulation is high and the calibration code is low. The improved SNR for each calibration code is described in Table 1,so the most suitable calibration code can be achieved. According to Equation (14),only when the parameter $K =$ 1 can we achieve the maximum signal-to-noise ratio and in other conditions,the more deviation from 1 the parameter $K$ is,the smaller the signal-to-noise ratio is. When the top plate sampling in Figure 11 and the calibration circuit in Figure 17 are employed,the parameter $K$ is changed to Equation (21). According to Equation (21) and Table 1,the value of $K$ is close to 1 with the increase of code,until the code is 1001. Then the $K$ will be less than 1. So the SNR changes in this way with the code.

A simulation result about the best fast case (fast process,lowest temperature,high voltage and minimum parasitic extraction) is shown in Figure 22(a) when the calibration code is 1101,and a simulation result about the worst slow case (slow process,high temperature,lowest voltage and maximum parasitic extraction) is shown in Figure 22(b) when the calibration code is 0011. The input voltage used in the worst slow case is halved because the output swing of OPA is restrained. In the two cases,the improved SNRs are 21.0574 and 21.0603 dB respectively,which shows the PVT variations are restrained by changing the calibration code. The mismatch is considered in the Monte Carlo simulation and the result is shown in Figure 23,where different calibration codes are used to obtain the best improved SNR. It should be noted that,in order to improve the simulation speed,the layout netlists of idle integrators are replaced by the capacitance model in the Monte Carlo simulation. However,the result still proves that the calibration circuit improves the mismatch to a certain degree.

5. Conclusion

In this paper,the impact of the parasitic phenomenon on the performance of an analog accumulator in the CMOS TDI image sensor is analyzed. In the basis,the impact of the parasitic phenomenon is decreased,eliminated and calibrated by the decoupling switch,the top plate sampling and calibration circuit respectively. A 128-stage optimized accumulator is designed based on 0.18-$\mu$m one-poly four-metal 3.3 V CMOS technology. The improved SNR of the proposed accumulator is obtained above 21.0574 dB in any situation. The linearity of the accumulator is 99.62% at the same time. The post layout simulation results have proved the effectiveness of the improvement for the accumulator when combating the parasitic phenomenon in the analog accumulator. Furthermore,it is possible to design a higher stage accumulator based on the proposed structure.