1. .Introduction
CMOS image sensors (CIS) have become promising candidates for solid-state imaging devices over charge coupled devices (CCD) due to the advantages of low power consumption,low cost,and advanced CMOS process compatibility[1, 2, 3]. Pinned photodiodes (PPD),regarded as the most outstanding photodetectors,have been widely employed by state-of-the-art CIS for a growing number of applications based on the strong superiority of the dark current reduction and other benefits[4, 5, 6, 7]. Nevertheless,they can suffer from the incomplete charge transfer due to the complicated electrical properties lying on the photocharge transfer path between the PPD and the floating diffusion (FD) node,thus triggering a critical image lag issue on subsequent frames[8]. One of the most common lag sources is the charge transfer potential barrier[9, 10, 11, 12] (CTPB) introduced in the overlapped area between the PPD and the transfer gate (TG). Traditionally,the height of the CTPB embedded inside the device tends to be evaluated with the help of a potential profile simulation through the TG channel by using TCAD tools as reported in References [10, 11, 12]. However,to the best of authors' knowledge,there has been little understanding up to now of how to experimentally measure the CTPB height.
In this paper,we propose a simple yet powerful method to measure the CTPB height by performing useful transformations on the sensor photoresponse curve under the steady-state illumination,thus providing a more persuasive and valuable evaluation of the CTPB height for guiding pertinently and accurately intrinsic-like charge transfer characteristics optimization in PPD-CIS. A steady and reasonable CTPB height of 48mV has been measured at various light intensity illuminations,through applying the measurement on a prototype PPD-CIS chip with an array of 160×160 pixels.
2. .Mechanism of the CTPB
A typical PPD-based pixel (normally called 4T-pixel) consisting of a PPD with a stack of P+/N/P structure and four func-tional transistors is shown schematically in Figure1. The PPD forms prior to exposure in a fully depleted region,in which the photocharge (electrons) could be collected and stored. The voltage of the FD node is reset to VDD by pulsing the reset transistor RST high. After a period of exposure,the collected photocharge packet is transferred from the PPD to the FD by switching on the TG transistor,and converted to a voltage sig-nal coupled on the FD capacitor. When the select switch SEL conducts,the converted voltage signal is buffered on the column bus by a connecting of a source follower SF.
Despite the existing works that have brought up the concept of the CTPB,the formation mechanism behind the CTPB in PPD-CIS is still to be understood and detailed to support our work physically. Based on a mainstream image sensor process,the buried N-type layer in the PPD is generally implanted subsequent to the polysilicon deposition by using a self-aligned process. It means that the whole N-type layer is isolated by the surface P+-type from the Si--SiO2 interface even within the PPD-TG overlapped area,where the photocharge would be transferred by. When the charge transfer mode is activated after exposure,the TG is pulsed high to establish an inversion NTG channel beneath the gate oxide. However,for pursuing the ultra-low dark current in a 4T-pixel[10, 13],a surface P+-type which has the doping concentration approximately 4--5 times higher than that of the P-substrate tends to be fabricated. In this case,the local P+-type in the PPD-TG overlapped area can hardly be inversed by the high TG pulse during the transfer period,thus remaining a particular P+-type region depleted or still accumulated. Then,a potential barrier (CTPB) is possibly introduced in the overlapped area according to the intrinsic differences of Fermi energy levels between the P-type and the N-type through the charge transfer path. The energy band diagram illustrated in Figure2 facilitates a physical comprehension of the CTPB formation. Notice that,Figure2(a) exhibits only the equilibrium state of the P+/NPPD (with a unified Fermi energy level),which in fact depends on the potential difference between P+ and NPPD as soon as the charge start to transfer. Figure3 shows a TCAD simulation of the potential profile through the transfer path during the charge transferring period in a deep submicron (DSM) process modeled PPD device. It can obvi-ously be observed that a CTPB-induced potential hump with a level of more than 100 mV is dropped in the PPD-TG overlapped area,which prevents the photocharge transferring from the PPD to the FD,resulting in residual (lag) charges in the PPD well.


3. .Principle of the proposed method
It is difficult to measure the CTPB embedded inside PPD-CIS straightforwardly. We focus on exploring an alternative method by utilizing the sensor photoresponse characteristics which could be easily measured. A potential diagram of the charge transfer path as the amount of the collected photocharge in the PPD well increases versus the exposure time is briefly shown in Figure4. Assuming the well capacitance is CPPD,the electrons with a number of N could thereby induce an increasing of the PPD internal potential by qN/CPPD,where q is the charge element. When the exposure time is short,the electron-induced qN/CPPD is much lower than the CTPB height (termed φb
Iiump=KT2exp(−qqN/CppD−φbkT), |
(1) |
Qjump=kT2exp(−qqN/CPPD−ϕbkT)tTG−ON, |
(2) |
where K is a physical constant depending on the material,tTG−ON
Iph=q∫λφ(λ)η(λ)dλ. |
(3) |
Therefore,the segment of the photoresponse curve in district III [see Figure5] would present a linear dependence of the output signal as a function of the exposure time according to:
dVdt=IphCGq, |
(4) |
φb=QresCPPD, |
(5) |
4. .Measurement and analysis
A prototype chip with an array of 160×160 6--pitch conventional PPD-pixels was fabricated using a DSM 1P4M CIS technology. The micrograph of the chip is shown in Figure6. Both schemes of the self-aligned process and a much higher surface P+-type doping level (3×
Figure8 shows the sensor photoresponse measured curves under different light intensity conditions of 0,10,100,and 1000 lux,and the corresponding CTPB-induced residual sig-nals are also marked according to the main idea of this paper. It is observed that,a fixed signal of≈

5. .Conclusion
An alternative measurement technique to extract the height of the CTPB embedded inside the photocharge transfer path in the PPD-CIS has been proposed by performing useful transformations on the sensor photoresponse curve. The method has been detailed theoretically and validated experimentally under various light intensity illuminations. The independence of the CTPB on light intensity has also been demonstrated. With the new technique presented in this paper,it becomes feasible to provide pertinently and accurately lag-free and high-speed sensors optimization with an insightful point of view.
6. .Acknowledgments
The authors would like to acknowledge Benlan Shen and Jiling Liu of LUSTER Light Tech.,Hui Yan of Xi'an Microelectronics Technology Institute,for their fruitful discussions.