1. Introduction

Optoelectronic devices have been widely used in communication, illumination, military, and material processing in the past decades. Extensive studies have shown that the performance, lifetime and cost of optoelectronic devices largely depend on the package technology^[1-3]. Specific to high-power laser diodes, which have been commonly used as efficient pumping sources for solid-state systems and fiber lasers, the market is looking forwards to higher power output and longer lifetime. The power level is usually limited by the catastrophic optical mirror damage (COMD) and thermal rollover, both of which are caused by the temperature rising of the active region. State-of-the-art laser diodes have electrical-to-optical conversion efficiency of up to 70% in labs^[4], while commercially available products have typical efficiency between 50% and 60%. Half of the power input has to be dissipated as waste heat, leading to considerable temperature rising in the active region under high-power operation. Moreover, efficiency is the function of the junction temperature, and decreases exponentially with increasing temperature, leading to more heat generated in the active region. This positive feedback results in COMD or thermal rollover, limiting the power output level of laser diodes. As to the lifetime, two main factors responsible for the failure of laser diodes are junction temperature and mechanical stress^[5]. Most of the stress is caused by the mismatch of the coefficient of thermal expansion (CTE) between the chip and the heat sink. During the die bonding process, the chip, solder, and heat sink cool from the melting temperature of the solder, leading to residual stress in assembly. The higher the CTE mismatch of the bonding components, the higher the maximum stress in the laser chip will result^[6]. In order to minimize stress in the laser chip, soft solder like indium, which could reduce stress by plastic deformation, was historically dominant in die bonding where copper was used as the mounting substrate. But soft solder has been proven to be sensitive to thermal fatigue and electro-migration^[7], in contrast to more reliable hard solder like eutectic gold-tin (AuSn) solder^[8]. However, AuSn solder cannot be used to bond a laser chip directly to a copper heat sink due to the high residual stress that it leads to. In most cases, this problem could be solved by using the so-called submount between the copper heat sink and the semiconductor laser chip when using AuSn solder^[9]. Submounts are usually made from materials differing little in CTE from the laser chips, but typically having a lower thermal conductivity than copper, leading to higher junction temperature and consequently deteriorated laser performance and shortened lifetime. The ideal submount would be highly thermally conductive and have CTE matched to the laser chip. In addition, it would be readily machined and available at low cost^[10]. Therefore, efficient thermal and mechanical management of submounts are needed for higher power output as well as longer lifetime.

In this work, the CTE-matched submount was designed as the sandwiched structure shown in Figure 1. A low-CTE middle layer is sandwiched between two high-CTE surface layers. When layers with different CTE are bonded together, the material with lower CTE will restrict the expansion (contraction) of the higher CTE material during heating up (cooling down), leading to the effective CTE at mounting surface matched to the laser chip. This three-layer structure is symmetric in order to avoid the bowing deformation. In addition, the heat transfer performance is enhanced due to the heat-spreading effect of the surface layer with high thermal conductivity. This structure offers great flexibility in material choice and design. Also, the production is less sophisticated and expensive, with respect to carbon materials and metal-matrix composites mentioned in Reference ^[11].

2. Numerical analysis of sandwich-structure submounts

Analytical solutions of thermal stress^[12] and temperature distribution^[13] are only available for simple models. Considering the complexity of model discussed here, the finite element method (FEM) was taken. All simulations were executed in a commercially available multiphysics finite element method solver, ANSYS 14.0. The detailed parameters required by mechanical and thermal simulations were listed in Table 1 and Table 2 respectively. The assembly comprises a laser diode, a submount, an F-mount copper heat sink. The laser diode under investigation is 5.5 × 0.5 × 0.105 mm³ GaAs-based chip. The F-mount copper heat sink is 8 × 22 × 2.5 mm³. The footprint of the submount is 5.75 × 4.5 mm², and the thickness of different layers is variable for calculations. Materials of the middle layer discussed here include aluminum nitride (AlN), silicon carbide (SiC) and molybdenum (Mo). Copper was chosen as the surface material for the properties of high conductivity, high CTE and easy fabrication by electroplating on both sides of the middle sheets. For simplification, half of the assembly was simulated due to the symmetry in lateral direction.

2.1 Mechanical analysis

The stress of laser diodes can be induced from epitaxial growth, wafer processing, and die bonding^[14]. The internal stress of the quantum well is caused by the lattice mismatch between the quantum well and bulk materials. In this paper, discussions were limited to stress which was introduced by die bonding process. Thus the laser chip was regarded as homogeneous material of GaAs. During packaging, the chip was firstly bonded with submount at 280 ℃ , the melting point of AuSn. Then the chip-submount assembly was connected with F-mount heat sink at 157 ℃ , using soft solder indium. Figures 2(a) and 2 (b) exhibit the stress intensity distribution before and after the secondary level packaging respectively. Comparison shows that, the maximum stress marked with "MX" in the pictures occurs at the interface between the surface and the middle layer of the submount. This mechanism releases the laser chip from excessive stress^[15]. The secondary level package introduces little stress to the laser chip due to the ductile characteristic of indium. Therefore the mechanical simulations were focused on the submounts.

To obtain the CTE-matched structure of the submount, the average CTE at the mounting surface (the region where the laser chip is soldered) was calculated. The relative dependence of the effective CTE on the vertical structure and middle material are illustrated in Figure 4. Analysis of results leads us to the following conclusions:

(1) The interpolated copper thickness is 0.039 mm for 0.3-mm Mo, 0.055 mm for 0.3-mm AlN, 0.073 mm for 0.3-mm SiC, corresponding to the CTE-matched locations indicated by open circles. It follows that SiC allows coating with the thickest copper under CTE-matched condition. Considering the thermal conductivity of copper is larger than these materials, the submount based on SiC is expected to have a better cooling effect than others.

(2) The change of CTE is larger for submounts made of AlN than the other materials at the surface copper thickness in the range of 0-1.5 mm. The adjustment of copper to CTE is more effective for the material with lower CTE as well as lower elastic modulus.

(3) The CTE increases with copper getting thicker in a fitted parabolic way. The corresponding copper thickness is 0.048 mm for 0.2-mm SiC, 0.072 mm for 0.3-mm SiC, 0.096 mm for 0.4-mm SiC at CTE-matched points. If the middle layer is thicker, the coated copper should be thickened to the same multiples to keep a fixed value of CTE. The thickness ratio of surface copper to middle layer is considered to be a more general parameter for CTE calculations. Given the CTE and elastic modulus of materials, certain thickness ratio will yield corresponding effective CTE at mounting surface of submount. This could be taken as the principle for adjusting the effective CTE to match the laser chip.

2.2 Thermal analysis

In most cases, the thermal performance of laser diodes can be described by thermal resistance, which is defined as:

${{R}_{\text{th}}}\text{=}\frac{\Delta T}{Q},$

(1)

wherein $\Delta T$ stands for the temperature difference between the active region and the heat sink, while Q means the thermal load of laser diodes. The smaller R_th is, the better the thermal performance of the device is. To evaluate the heat-dissipating capability of the submounts, thermal resistance of the device was calculated. A laser diode of 55% electrical-to-optical conversion efficiency and 20 W output power level was chosen for thermal modeling. The emitting aperture of the laser was 100 μm. The active region was set to be the only heat source, due to nonradiative recombination and reabsorption of radiation, and the minor impact of Joule heat was ignored^[16]. The convective cooling was presented at the exterior of the laser chip, the convection coefficient was taken as 25 W/(K·m) and the temperature of the air was 20 ℃. The lower basal plane of the copper F-mount was taken to be constant at 20 ℃, as the boundary condition.

In thermal analysis, the heat generation was limited in a small volume of the active region. Also, thermal conductivity of epitaxial layers differed a lot from each other. Thus regarding the laser chip as homogeneous material of GaAs like we did in mechanical simulations was not appropriate. Therefore, the detailed epitaxial structure was employed which is listed in Table 2. The main problem that made the model challenging was the extremely stiff aspect ratio. The active-region thickness is in nanometer scale while the device dimensions are in millimeter level. In order to solve the problem accurately, fine mesh would be required which demands too much memory. This problem was solved by "submodeling method" in this work. Finer mesh was created around the active region, and the bottom of the laser diode was used as the cut boundary which specified the calculated temperature of the coarse model as the boundary condition for the submodel. By this submodeling method, the thermal behavior of the assembly was simulated and shown in Figure 5. Figure 5(b) is the more accurate temperature distribution of the laser chip which is based on the coarse model in Figure 5.

The dependence of thermal resistance on the submount is demonstrated in Figure 5. From these results, some conclusions can be drawn:

(1) It is demonstrated in Figure 5(a) that, with the coated Cu increasing from 0 to 0.15 mm, thermal resistance decreased by 3% for the submount made of SiC, 7.6% for the submount made of AlN, 12.8% for the submount made of Mo. This means that the enhanced cooling effect of surface copper becomes stronger with the thermal conductivity of the middle material getting lower.

(2) When CTE-matched with GaAs, the Cu-SiC material combination provides the lowest thermal resistance. At CTE-matched open circles indicated in Figure 4(a), the interpolated thermal resistance for the SiC-based submount is 2.57 K/W, for the AlN-based submount is 2.74 K/W, and for the Mo-based submount is 2.91 K/W. Actually, the submount based on SiC keeps the lowest R_th over the whole range due to the highest thermal conductivity of SiC.

(3) Increasing the copper thickness enhances the heat-spreading effect and reduces the temperature of the active region, as would be expected. Thermal resistance decreases from 2.67 K/W at the surface copper thickness of 0 to 2.5 K/W at the surface copper thickness of 1.5 mm (when the middle layer is set to be 0.3-mm SiC). After the copper thickness exceeds 0.09 mm, thermal resistance decreases by less than 0.2% for every incremental step, indicating it is unreasonable to further thicken the surface copper for the middle-layer thickness in the range of 0.2-0.4 mm.

(4) Fixed surface thickness at 0.09 mm, thermal resistance increases from 2.49 K/W at the middle thickness of 0.2 mm to 2.52 K/W at the middle thickness of 0.3 mm, then to 2.56 K/W at the middle thickness of 0.4 mm. Because thickening the middle layer would increase the thermal path from the active layer to the F-mount, leading to temperature rising of the active region.

3. Conclusions

Sandwich-structure submounts for high-power single emitters were studied. The thermal expansion behavior and heat dissipating capability of submounts were simulated. The numerical results demonstrated that, effective CTE at mounting surface could be adjusted to match the laser chip by changing the thickness ratio of surface layer to middle layer. SiC is the most promising material candidate for the middle layer compared with AlN and Mo, from the view of thermal management. In the practical design of submounts, thicker copper and thinner middle material is preferred to minimize the junction temperature. However, the upper limit of this thickness ratio is determined by the CTE-matched requirements. Thus a good balance needs to be achieved to obtain reasonable CTE as well as efficient heat dissipation during the submounts' design. Further experiments are required to verify the effect of submounts on the output power and lifetime of high-power laser diodes.