1. Introduction

The modern power semiconductor industry requires high efficiency and fast switching devices for various applications such as power transformation and control,communicational radar and so on. High speed and low loss are paramount for the mentioned components. A Schottky diode operated with majority carriers is an ideal low blocking voltage,forward current density and ultra-fast switching device. The switching speed of the device can be enhanced by the lifetime engineering using methods such as gold doping or electron irradiation to reduce the lifetime of minority carriers,however it will restrict conductivity modulation in forward conducting while raise the forward voltage drop (V_F),which increases forward conduction loss,and thus results in a trade-off between switching speed and the V_F. A type of diode with low loss and fast recovery was developed by using a p⁺/n⁺ mosaic structure (MS,also known as "ideal ohmic contact") to accelerate the switching speed^[1]. A new rectifier of merged p-i-n/Schottky (MPS) structure based on integrating a Schottky contact region with a p⁺/n junction grid structure was proposed for improving the forward and switching characteristics of high-voltage rectifiers^[2]. A type of 4H-SiC junction barrier Schottky (JBS) rectifier with sandwich p-type well (SPW JBS) was developed,where the top and bottom of p⁺ grids are replaced by low-doped p region based on the common JBS rectifier^[3],which shows an improvement in breakdown voltage and a significant decrease in reverse leakage current density. An ideal ohmic contact with the n⁺ region substituted by p⁺/n⁺ MS for the p⁺(SiGe)-n^--n⁺-type diode was designed^[4],its reverse recovery characteristics were further improved without notably sacrificing the V_F,the reverse block voltage was very sensitive to the base region thickness while the reverse recovery current (I_rr) did little. Simulation on reverse recovery waveforms under both resistive and inductive switching conditions for Si material p⁺-n^--n⁺-type diode with MS and non-MS in cathode was carried out^[5],which reflects that the increase of area ratios of p⁺ region to n⁺ one in MS shortens the reverse recovery time (t_rr),however the MS cannot change the sweeping mechanism for the minority carriers in the base region. The MS was formed on the anode of p⁺-p^--n⁺-type Si diode by selective phosphorus diffusion and boron diffusion through its corresponding oxide mask separately^[6],which showed that the V_F of the MS diode is lower than that of the conventional one at nominal current,while no significant over-voltage peak is presented in forward recovery behavior. A comparative study of a modified p-i-n diode versus modified MS p-i-n rectifier was performed by technology computer-aided design (TCAD) to demonstrate that^[7],the reduction of value of t_rr in the latter is mainly due to less stored charges in base region than that in the former,the V_F of the latter is not quite affected by different mosaic area ratios,the latter exhibits a better trade-off between the V_F and switching characteristics compared to the former. Using a method of local lifetime control,the strategy of trade-off between the t_rr and the V_F,softness factor as well as backward leakage current was discussed via numerical simulation^[8]. Optimizing effects on device performance from emitter efficiency engineering and local lifetime one were compared^[9].

Recently,high mobility nanocrystalline Si (nc-Si) films have widely drawn attention ^{[10, 11]},and the heterojunction devices of crystalline/nanocrystalline Si were developed^{[12, 13]}. In this work,heavily boron- and phosphorus-doped nc-Si films were severally deposited on the lithography mask etched p⁺- and n⁺-type Si sides of p⁺-n^--n⁺-type diode to form a device with mosaic anode and mosaic cathode rather than p⁺-type anode and n⁺-type cathode separately. Electrical measurement results imply that the performance of mosaic diode is better than that of conventional one without mosaic electrode.

2. Experimental details

A double-facet polished n^--type $\langle 111\rangle$ Si wafer with around 220 μm thickness and 20 Ω⋅cm $({{N}_{\text{D}}}\tilde{\ }2\times {{10}^{14}}c{{m}^{-3}})$ average resistivity was used as substrate. The first type of p⁺-n^--n⁺-type diode without MS shown in Figure 1(a) was prepared with epitaxial process. Namely,a heavily phosphorus-doped Si layer with 6 mΩ⋅cm resistivity (donor concentration $N_{\rm D}\sim 1\times 10^{{19 }} cm^{{-3}})$ and 2 μm thickness was grown on one side of the substrate at temperature 1500 K. Subsequently,a heavily boron-doped layer with 2 μm thickness and 90 mΩ⋅cm resistivity (acceptor concentration $N_{\rm A}\sim 1\times 10^{{18 }} cm^{{-3}})$ was deposited on the other side of the wafer at the same temperature. Based on the first device,without altering the cathode,the p⁺-type Si layer was etched by lithography mask to make an array of square wells $(10\times 10 \mu m^{{2}})$ with 2 μm depth and spacing distance 40 μm. Hereafter,phosphorus-doped Si film was deposited by phosphine PH₄ and silane SiH₄ mixed gas with 3.0 vol% doping ratio (i.e.,PH₄/SiH₄ in volume percentage) in the wells to form the mosaic anode. Thus the second type of component with mosaic anode was obtained,as exhibited in Figure 1(b). The deposition process was operated in a capacitively coupled radio-frequency (RF of 13.56 MHz) plasma-enhanced chemical vapor deposition (PECVD) system aided with direct current (DC) bias stimulation. It is worth specially emphasizing that the SiH₄ was strongly diluted to 1.0 vol% in hydrogen H₂,the latter acted as carrier gas. The other process parameters were chosen as follows: the RF power density $0.6\pm 0.05 W/cm^{{2}}$ ,reactant gas pressure $100\pm 5$ Pa and a negative bias $-200\pm 2$ V applied to the substrate,the substrate's temperature was maintained at $523\pm 3$ K. The deposition process under low temperature is beneficial to energy saving. Based on the second diode,the n⁺-type Si layer was etched by lithography mask to make the same array as those in the p⁺-type layer. Thereafter,boron-doped Si film was deposited by diborane B₂H₆ and silane SiH₄ mixed gas with 3.0 vol% doping ratio in the wells to form the mosaic cathode. Thus the third type of diode with mosaic anode and mosaic cathode was obtained,as demonstrated in Figure 1(c). AuCr and AuGe alloy films as ohmic contact electrodes were prepared by electron-beam evaporation on the anodes and cathodes of these three types of diodes respectively for electrical measurement. The processes of PECVD and electron-beam evaporation were practically illustrated in our previous works ^{[12, 13]}.

As shown in Figure 2(a) and (b),structures of the prepared films using PECVD were checked by a high resolution transmission electronic microscope (HRTEM,JEM-2010 type) with operation voltage of 200 kV. Mean size of about 5.0 nm of crystallites in different films was evaluated by the taken photographs,which shows the films were nanocrystallized. As presented in Figure 2(c),X-ray diffraction (XRD) patterns from the films were taken by a Rigaku RINT 2500 diffraction meter with Cu kα₁ radiation in standard $\theta -2\theta$ configuration The diffraction peaks (111),(220) and (311) reveal nanocrystallization in the fabricated specimens,called the nc-Si films. Average size of around 4.5 nm of Si nanocrystals in different films was calculated by the Scherrer formula based on the full width at half-maximum (FWHM) of the (111) diffraction peaks. The size difference between HRTEM evaluation and XRD one can be allocated to without subtracting the aberration of XRD patterns arising from instrumental and experimental factors,it coincides with another demonstration^[14].

At room temperature,concentration n of majority carriers and Hall mobility μ in van der Pauw-type boron- and phosphorus-doped nc-Si samples were checked by a HALL8800 type computer-controlled Hall effect meter operating in strong magnetic field (B=4000 Gauss) from an electromagnet excited by direct current I_E. In order to obtain the Hall voltage V_H with eliminating the influence from Righi-Leduc effect,Nernst effect,and potential of non-equal position,symmetrical measurement conditions of injected direct current ( $\pm I_{\mathrm{S}}= \pm5$ mA),applied magnetic field (±B,by altering the I_E direction) and data processing method were adopted,also the impact of voltage V_E originating from Ettingshausen effect on V_H was ignored due to $V_{\mathrm{E}}\ll V_{\mathrm{H}}$ ^[10]. Thus the Hall coefficient R_H and n can be calculated by the formul as R_H=dV_H/(I_SB) and $n=1/(\left| {{R}_{\text{H}}} \right|q)$ ,where d is the film thickness,q is the elementary charge. Further,conductivity $\sigma =(L{{I}_{S}})/(S{{V}_{\text{L}}})$ of the samples can be calculated after taking the voltage V_L between two ohmic contact points with spacing distance L along the I_S direction,cross sectional area S=bd Where b is the width of sample,here sets as b=L= 5 mm,therefore Hall mobility μ was evaluated by the relation of $\mu =\sigma /({nq})$ . These Hall effect experimental results are demonstrated in Table 1. Using a HP4280A-type precision LCR meter,capacitance-voltage (C-V) relations of the fabricated (n^-)Si/(p⁺)nc-Si and (n^-)Si/(p⁺)nc-Si junctions were measured by means of a DC-biased small AC signal (5 mV) of 1 MHz frequency,as displayed in Figure 3. Forward and backward current density-voltage (J-V) characteristics of the prepared diodes were probed by a computer-controlled system including a HP4140B type PA meter and a DC voltage source,as depicted in Figure 4. Waveforms of reverse recovery current I_rr and reverse recovery voltage V_rr in Figure 5 were detected by an inductive switching circuit and were displayed by a GDS-3504 type oscilloscope,the details can be found elsewhere^[15]. Test conditions were set as forward current intensity I_F= 3 A,backward biased voltage V_R=-30 V and current commutating rate dI_f/dt=200 A/μs.

3. Results and discussion

3.1 Capacitance-voltage characteristics

C-V data were measured to determine whether the fabricated structures of (n^-)Si/(p⁺)nc-Si and (n^-)Si/(n⁺)nc-Si form as semiconductor junctions,as exhibited in Figure 3. One can fit two lines according to the data derived from the structures respectively,the voltage axis intercepts of these plots indicate a built-in potential V_bi of about 0.80 V for the (n^-)Si/(p⁺)nc-Si and (n^-)Si/(n⁺)nc-Si,which verifies the formation of semiconductor junctions. The detected value 0.80 V is slightly higher than 0.70 V of the Si p/n junction,which can be assigned to the fact that the bandgap of nc-Si is wider than that of crystalline Si ^[12]. The slope of fitted line according to data from (n^-)Si/(n⁺)nc-Si junction demonstrates almost the same as that from (n^-)Si/(p⁺)nc-Si,which can be explained by the formula of depletion layer capacitance C in abrupt junction, $C^{{2}}=A^{{2}}(q\varepsilon n_{\mathrm{i}}/2)/(V+V_{\mathrm{bi}}-2\textit{kT}/q)$ ,where A is the junction area,q is the elementary charge,ε is the dielectric constant of Si,n_i is the carrier concentration in (n^-) k is the Boltzmann constant and T is the measurement temperature. As illustrated by Hall effect results in Table 1,the concentrations of carriers in (n₊)nc-Si and p₊nc-Si separately are much larger than the one in (n_-)Si of base region,the depletion layers of two junctions are both located primarily at (n_-)Si side,namely,two depletion layers belong to an identical material although they are distributed respectively in two borders of base region. Hence,slopes of the two fitted lines show little difference. The formed junctions play an important role in static and dynamic conduction behavior in the operating mosaic diodes,as clarified in the following sections.

3.2 Forward static J-V relations

The forward current density-voltage (V_F-V) characteristics of the investigated devices are shown in Figure 4(a). One can find that the forward voltage drop V_F of these diodes is almost the same,which can be attributed to the V_F being mainly decided by the identical base region thickness of these devices. However,the J_F-V feathers of mosaic diodes degrade when the values of J_F are higher than about 100 A/cm²,which can be comprehended by the fact that the effective areas of mosaic anode or cathode are less than those of traditional electrodes due to (n⁺)nc-Si embedded in the anode while (p⁺)nc-Si inserted in cathode. When the MS diodes are forward biased,the majority carriers are limited to enter base region with a result of conductivity decrease,called the emitter efficiency control. With the forward applied voltage V below 0.35 V,the J_F illustrates proportionally to V,which can be assigned to a resistive shunt across the (n⁺)nc-Si/(n^-)Si junction in the anode and the (n^-)Si/(p⁺)nc-Si one in the cathode. The built-in electrical field ${{E}_{\text{BI}{{\text{1}}^{\prime }}}}$ formed in (n^-)Si/(n⁺)nc-Si drove holes into the base region while the ${{E}_{\text{BI}{{\text{2}}^{\prime }}}}$ formed in (n^-)Si/(p⁺)nc-Si drove electrons into there. This phenomenon was supported by another analysis^[16]. In the voltage range from about 0.4 to 0.70 V,the measured data agree well with the formula governed by diffusion principle, ${{J}_{\text{F}}}={{J}_{\text{s}}}({{e}^{qV/kT}}-1)$ ,for low-level injection into base region in diode,where J_s is the reverse saturation current density. As the voltage is over 0.75 V,the observed data comply with another expression dominated by recombination mechanism, ${{J}_{\text{F}}}=(2q{{D}_{\text{a}}}{{n}_{\text{i}}}/l)F(l/{{L}_{\text{a}}}){{e}^{qV/2kT}}$ ,for high-level injection,where D_a and L_a are the ambipolar diffusion coefficient and diffusion length,respectively,l is the half of drift region length.

3.3 Backward static J-V characteristics

The backward J_R-V relations of the studied diodes are exhibited in Figure 4(b),where the strong field dependent J_R-V features indicate that the reverse current density J_R of the devices with and without MSs is apparently dominated by the field-assisted thermal generation mechanism in the depletion region until avalanche breakdown sets on at about 1400 V,as endorsed by another experiment^[17]. One can see from Figure 4(b) that the reverse leakage current reduces notably when the MSs are introduced in the anode and cathode separately. This can be comprehended from the Figure 1(c),where one can find that the directions of the built-in electrical field E_BI1′ and E_BI2′ formed in (n^-)Si/(n⁺)nc-Si and (n^-)Si/(p⁺)nc-Si junctions are opposite to the ones of E_BI1 and E_BI2 in (n^-)Si/(p⁺)Si and (n^-)Si/(n⁺)Si junctions. When the diodes are biased by backward voltage,the field in (n^-)Si/(p⁺)nc-Si and (n^-)Si/(n⁺)nc-Si junctions obstructs the conduction of minority carriers (holes) with a result of smaller leakage current. Accordingly,the safe operating area of the device can be expanded. A drawback of the diodes inserted mosaic is indicated in Figure 4(b) that the reverse breakdown voltage decreases. When the mosaic diodes are backward biased,the E_BI1′ and E_BI2′ against the external electrical field from biased voltage,thus the breakdown voltage is decreased. On the other hand,when mosaic electrodes substitute the conventional n⁺- and p⁺-type ones in the device,the effective areas of (n^-)Si/(n⁺)Si and (n^-)Si/(p⁺)Si junctions are reduced,impact ionization occurs more easily under backward high voltage condition while it weakens the reverse blocking voltage.

3.4 Reverse recovery behaviors

The reverse recovery current I_rr and voltage V_rr characteristics of the fabricated devices are represented in Figure 5. It can be seen from there that the values of maximum reverse recovery current I_rrm,peak reverse recovery voltage V_rrm and the reverse recovery time t_rr for the conventional device are the largest,while those for the diode with mosaic anode and mosaic cathode are the smallest,also the surge in waveforms of I_rr and V_rr is notably suppressed,which implies that mosaic devices are very useful for the low loss modules. As the MS was adopted in the anode of p-i-n diode,the emitter efficiency for the holes was controlled,thus fewer holes are injected into the base region. The electron concentration from the cathode side must drop to maintain quasi-neutrality. This will reduce the concentration of majority carriers while resulting in a decrease of minority carriers stored in the base region of diode,as a consequence of decrease in I_rrm and t_rr. Furthermore,the implantation of (n⁺)nc-Si in (p⁺)Si will reduce the capacitance and voltage drop of anode junction (p⁺)Si/(n^-)Si owing to depletion between (n⁺)nc-Si and (p⁺)Si,hence the surge in the waveforms of I_rr and V_rrm is restrained. With the mosaic anode and cathode employed synchronously,fewer holes and electrons are separately injected from anode and cathode,accordingly fewer minority carriers are stored in the base region with a result of decrease in I_rrm and t_rr. Moreover,when a (p⁺)nc-Si/(n⁺)Si mosaic electrode replaces the conventional n⁺ one,in reverse recovery process,the minority carriers (holes) arriving at the border are extracted smoothly into p⁺ regions by the built-in field $(E_{\mathrm{BI2^\prime }})$ in (n^-)Si/(p⁺)nc-Si junction,as shown in Figure 1(c),which further reduces the t_rr. As indicated by Hall effect measurement,it is just because of the high carrier mobility involved in the (p⁺)nc-Si layer,minority carriers (holes) can quickly pass through there in reverse recovery period,hence shortening the t_rr. The relatively high mobility in the (p⁺)nc-Si films can be attributed to very thin boundaries between nanocrystallites,as illustrated by the HRTEM images in Figure 2(a) and (b). In addition,enhancement of sweeping out minority carriers accelerates the form of space charge region across anode and cathode junctions,thus facilitates to stabilize the V_rr and I_rr as early as possible,and the soft recovery process can also be realized.

One can find from Figure 5 that the I_rrm and zero crossing of voltage across diode do not exactly occur at the same time,which can be explained by the ramp recovery characteristics of the fabricated diodes depending significantly on the circuit operation conditions,which coincides with another study^[18].

4. Conclusion

A mosaic electrode of crystalline/nanocrystalline Si was successfully utilized in a power diode fabricated by epitaxial technique and PECVD to improve the reverse recovery performance. The reverse recovery time,the peak reverse recovery current and voltage as well as the surge in reverse recovery process were depressed,which can be mainly assigned to the mechanism of emitter efficiency control. Little variation of forward voltage drop can be allocated to conductivity modulation effect in wide base region without any influence from electrodes. With reverse biasing of the mosaic diodes,the built in electrical field in (n^-)Si/(p⁺)nc-Si and (n^-)Si/(n⁺)nc-Si junctions is against the external one,therefore the leakage current was limited while the backward breakdown voltage was deteriorated.