1. Introduction

The analog front end (AFE)^[1-9] is a key part of the processor for reading and processing an analog signal. The relevant research receives more and more attention from researchers. In imaging and video applications, such as satellites, airport and industry, a charge coupled device (CCD) is used widely ^{[10, 11]}. For video AFE^{[12, 13]}, as a key part for processing CCD output signal, its performance limits the quality of image largely. Therefore AFEs for CCD and Digital Image Sensor arrays have been researched for the last fifteen years. Many systems had been proposed in various works^{[14, 15]}. However, due to limitations in the integration, resolution and dynamic range, they could not satisfy requirements perfectly. Therefore, it is very meaningful to design a high-resolution and high-speed AFE with larger dynamic range. This paper proposes a novel, monolithic 14-bit 40-MHz AFE which could deal with the maximum CCD output signal reaching 2 V.

In this work, a highly integrated, single-chip CCD AFE based on the following design techniques is proposed. First, a digitally controlled wideband, high-performance VGA is designed to regulate the input signal to the maximum dynamic range. Second, a novel CDS takes image information out of noise, and amplifies the signal accurately with 9-bit programmable gain ranging from 0 to 18 dB in 0.035 dB step. Third, an effective and high-resolution 14-bit ADC is obtained by careful design. Fourth, a precision timing core based on the DLL (delay locked loop) theory with the pixel-period clock as reference can provide the 48 phase clocks with 520 ps adjacent interval. With the help of a clock assembling circuit which is controlled by registers, the system can provide adjustable clocks for CDS, ADC and CCD arrays. Meanwhile, a programmable driving-strength control circuit is adopted for the reset clock and horizontal clock. Finally, a high-speed LVDS I/O interface is designed to get fewer pins and lower noise.

2. AFE architecture

The proposed AFE features a complete, highly integrated system which was designed to sample and quantify output signals from CCD arrays. Figure 1 shows the block diagram of the AFE. The 14-bit parallel digital outputs were converted into serial differential outputs with the help of LVDS. The internal registers are programmed by an image processor (outside chip) through 3-wire serial interface (SL, SDATA and SCLK), so as to provide variable gain adjustment, programmable correlated double sampling clock, and so on. As shown in Figure 1, the signal CCD_SIGNAL from CCD arrays is coupled by capacitance (outside chip). The input common voltage of VGA is set by DC clamping. The proposed VGA amplifies input signal in a gain range -1.08 to 41.06 dB with 6.02 dB step. The CDS samples the pixel data of CCD reference level and data level, which contain nearly the same noise contribution. As shown in Figure 2, through sampling in two phases achieved by SHP and SHD, we can get the CCD signal with lower noise in one pixel period. Meanwhile, the proposed CDS provides the programmable gain with smaller gain step.

When the magnitude of CCD signal is much smaller than the optimal signal level, the reconstructed images from the converted digital data are too dark and image recognition is almost impossible. The external imaging processor analyses the AFE outputs and generates proper gain control signal to adjust gain of VGA and CDS separately. So the subsequent ADC can always have an input signal with maximum dynamic range to quantify. Superior to other CCD AFEs which have 1 V_P-P input dynamic range or less than 1 V_P-P, the proposed AFE can quantify the maximum CCD signal reaching 2 V_P-P. So it can satisfy various CCD sensors applications. In addition, in Figure 2, RG and H2/H4 (reverse to H1/H3) are the reset clock and horizontal control clock for CCD arrays, respectively. CLK_ADC is the main clock for 14-bit ADC to quantize the analog signal.

2.1 Digitally controlled wideband variable gain amplifier

A variable gain amplifier (VGA)^{[5, 17]} is usually employed in the ADC to maximize the dynamic range. The gain of the proposed VGA is digitally controlled by processors outside to maintain the signal level at a suitable level for the data converter. The subsequent CDS can further regulate the signal with a more precise gain step of 0.035 dB. Finally, the input signal of ADC can reach the maximum value accurately.

The VGA described here has a gain range from -1.08 to 41.06 dB with 6.02 dB step. It comprises a gain attenuator from 0 to -42.14 dB followed by a high-speed fixed-gain amplifier. In this way, the amplifier does not need to cope with large inputs and can benefit from the use of negative feedback to precisely define the gain. More important is the truth that the bandwidth of the amplifier keeps constant with no influence from variation of gain. Most variable-gain amplifiers obtain the varying gain through changing the value of feedback resistance. So the bandwidth would vary with the gain. The circuit proposed here solves this problem perfectly. The attenuator is realized as a 7-stage R-2R ladder network. The voltage ratio between all adjacent taps is exactly 2, or 6.02 dB. This provides the basis for the precise linear-in-dB behavior. In addition, since both the attenuator and the amplifier with negative feedback are essentially linear elements, distortion can be arbitrarily low.

To obtain the maximum gain, the fixed gain of the closed-loop amplifier should be equal to 41.06 dB. Thus the feedback factor f can be calculated as follows:

$f\approx {{10}^{\frac{{{A}_{\text{closed}}}}{20}}}\approx \frac{1}{113},$

(1)

where A_closed is the gain of closed loop amplifier. With the consideration of 40 MHz closed-loop application, the unit-gain bandwidth of a single-stage amplifier should reach 4.52 GHz. To achieve better performance in linearity, the open-loop gain of the amplifier should be high. Meanwhile, the output swing should be large for maximizing the dynamic range. Combined with the requirements mentioned above, a three-stage amplifier should be used. The structure of the amplifier adopted in the VGA is shown in Figure 3.

The amplifier consists of three stages. The preamplifier is designed to improve the transconductance of the main amplifier. The transconductance of the front two-stage amplifier can be obtained as follows:

${{G}_{\text{m}}}={{A}_{\text{p}}}{{g}_{\text{m6}}},$

(4)

where A_P is the gain of the preamplifier. In this design, the A_P is 2.49, or 7.938 dB. The main amplifier is a single-end output amplifier with gain-boost structure for higher gain. The third-stage amplifier could provide the large output swing, and high driven strength. However, the poles introduced by three stages would bring large degradation in the performance of frequency, leading to the problem in stability. Therefore, the frequency compensation is necessary. As the dotted line shows in Figure 3, the Miller compensation capacitance adopted in the proposed amplifier is connected to the point B in the source of MOSFET M11, instead of the point A in the output of the second-stage amplifier. Being superior to the traditional Miller compensation method, the zero brought about by this way can increase by g_mllR_eq times in the frequency (R_eq is the output impedance of the main amplifier). Since the second-stage amplifier is single-end output amplifier, it is unavoidable that the high-swing current mirror would generate poles and zero. It will bring about a terrible effect in the bandwidth of the amplifier. The proposed amplifier utilizes a very simple and powerful method tostabilize bandwidth. Introducing a compensation resistor R between the gates of M14 and M15 can bring an obvious enhancement in bandwidth. The introduction of resistor R creates a new pole and zero. A maximum bandwidth can be obtained when zero cancels the low-frequency pole.

Finally, the proposed amplifier can obtain an open loop gain of 123.1 dB and a bandwidth of 172.2 MHz (@41.06 dB). And in 172.2 MHz, the phase margin of the amplifier is 69.9 degrees. The simulation results are shown in Figure 4. The plots indicate that the design could satisfy the requirement of VGA very well. The summary of transistor sizes and values of the passive elements are shown in Table 1.

2.2 Correlated double sampler with variable gain amplifier

Normally the CCD input signal which consists of noise and data information is amplified simultaneously. The CDS can separate the data information from the noise effectively and further amplify the signal. Different from the previous AFEs which have CDS and VGA separately, the circuit proposed in this paper has a CDS integrated with the VGA functionality through changing the value of capacitor via the use of capacitors array. Through this method, we can modulate the closed-loop gain of the CDS linearly. Figure 5 shows the proposed CDS structure. CCDIN is input signal. V_refT, V_refB and V_refM are reference voltages of 2, 1 and 1.5 V from voltage reference. CDS samples the single-end signal CCDIN and outputs the differential signal to the 14-bit ADC. The capacitors array in the dashed line region shown in Figure 5 is used to modulate the closed-loop gain of CDS to get the VGA functionality. The capacitors array is divided into nine parts. Each part has a different quantity of unit capacitor according to the weight of the corresponding control bit. For example, D_A0 is the lowest bit in four-bit data of D_A0-D_A3 which control one unit capacitor. D_B4 is the highest bit in five-bit data of D_B0-D_B4 which control sixteen unit capacitors. The state of the switch in each part is controlled by the corresponding control bit. Thus we can get programmable gain through nine control bits: D_A0-D_A3, D_B0-D_B4.

In Figure 5, K1 is controlled by SHP clock signal, achieving the sampling for the reference level which contains the noise. K2 is controlled by SHD clock signal, achieving the sampling for the signal level which contains the same noise as the reference level. Meanwhile, K2 finishes the subtraction of two sampling values to get the data information component of the CCDIN. As shown in the Figure 2, K1 (SHP) and K2 (SHD) are two phase non-overlapping clocks.

The differential output voltage of CDS can be calculated as follows:

${{V}_{\text{o+}}}-{{V}_{\text{o-}}}=1-\text{Gain}\cdot (\text{CCDI}{{\text{N}}_{\text{SHP}}}-\text{CCDI}{{\text{N}}_{\text{SHD}}}),$

(3)

$\text{Gain}={{N}_{2}}/{{N}_{4}}.$

(4)

CCDIN_SHP stands for the reference level of CCDIN in the SHP sampling time. CCDIN_SHD stands for the signal level of CCDIN in the SHD sampling time. V_o+ and V_o- represent the differential outputs of CDS, respectively. In Equation (4), N₂ and N₄ are two parameters related to capacitor array as follows:

$\begin{align} & {{N}_{2}}=[C\cdot (\overline{{{D}_{\text{B0}}}}\cdot {{2}^{0}}\text{+}\overline{{{D}_{\text{B1}}}}\cdot {{2}^{1}}\text{+}\overline{{{D}_{\text{B2}}}}\cdot {{2}^{2}}\text{+}\overline{{{D}_{\text{B3}}}}\cdot {{2}^{3}} \\ & +\overline{{{D}_{\text{B4}}}}\cdot {{2}^{4}})+{{C}_{\text{in}}}]{{({{C}_{\text{AB}}})}^{-1}} \\ & +[C\cdot (\overline{{{D}_{\text{A0}}}}\cdot {{2}^{\text{0}}}\text{+}\overline{{{D}_{\text{A1}}}}\cdot {{2}^{1}}+\overline{{{D}_{\text{A2}}}}\cdot {{2}^{2}}\text{+}\overline{{{D}_{\text{A3}}}}\cdot {{2}^{3}})] \\ & \times [C\cdot (\overline{{{D}_{\text{A0}}}}\cdot {{2}^{\text{0}}}\text{+}\overline{{{D}_{\text{A1}}}}\cdot {{2}^{\text{1}}}\text{+}\overline{{{D}_{\text{A2}}}}\cdot {{2}^{2}}\text{+}\overline{{{D}_{\text{A3}}}}\cdot {{2}^{3}}) \\ & +{{C}_{\text{A}}}+C\cdot ({{D}_{\text{A}0}}\cdot {{2}^{0}}+{{D}_{\text{A1}}}\cdot {{2}^{\text{1}}} \\ & +{{D}_{\text{A2}}}\cdot {{2}^{2}}+{{D}_{\text{A3}}}\cdot {{2}^{3}})+{{C}_{\text{AB}}}{{]}^{-1}}. \\ \end{align}$

(5)

$\begin{align} & {{N}_{4}}=[{{C}_{\text{B}}}+C\cdot ({{D}_{\text{B0}}}\cdot {{2}^{0}}+{{D}_{\text{B1}}}\cdot {{2}^{\text{1}}}+{{D}_{\text{B2}}}\cdot {{2}^{2}} \\ & +{{D}_{\text{B3}}}\cdot {{2}^{3}}+{{D}_{\text{B4}}}\cdot {{2}^{\text{4}}})+{{C}_{\text{f}}}]{{({{C}_{\text{AB}}})}^{-1}} \\ & +[{{C}_{\text{A}}}+C\cdot ({{D}_{\text{A}0}}\cdot {{2}^{0}}+{{D}_{\text{A1}}}\cdot {{2}^{\text{1}}} \\ & +{{D}_{\text{A2}}}\cdot {{2}^{2}}+{{D}_{\text{A3}}}\cdot {{2}^{3}})] \\ & \times [C\cdot (\overline{{{D}_{\text{A0}}}}\cdot {{2}^{0}}\text{+}\overline{{{D}_{\text{A1}}}}\cdot {{2}^{\text{1}}}\text{+}\overline{{{D}_{\text{A2}}}}\cdot {{2}^{2}} \\ & +\overline{{{D}_{\text{A3}}}}\cdot {{2}^{3}})+{{C}_{\text{A}}}+C\cdot ({{D}_{\text{A}0}}\cdot {{2}^{0}}+{{D}_{\text{A1}}}\cdot {{2}^{1}} \\ & +{{D}_{\text{A2}}}\cdot {{2}^{2}}+{{D}_{\text{A3}}}\cdot {{2}^{3}})+{{C}_{\text{AB}}}{{]}^{-1}}. \\ \end{align}$

(6)

From the above equations, the gain of CDS is programmed by the 9-bit control register. Furthermore, we can get the following equation:

$20\lg (\text{Gain})\simeq 18-0.035\times \text{Code}.$

(7)

According to the relationship between gain and binary number indicated in Equation (7). It is known that the CDS proposed in this paper has a good linear gain performance and a high gain resolution of 0.035 dB in the range 0-18 dB.

2.3 14-bit 40-MHz ADC

As shown in Figure 1, a typical 14-bit 40-MHz pipeline ADC with redundancy calibration is adopted to transfer the analog input into digital code. Through using redundancy calibration, the comparator offset error can be eliminated partly. To reduce power and design complexity of ADC avoiding degradation in performance, the proposed ADC adopts the optimization design in the numbers of conversion stages and resolution per stage.

In Figure 1, key parts of each stage in ADC are described. The structure from the first stage to the kth stage is same, which contains the sub-ADC, sub-DAC and residual amplifier. So the total power of ADC is equal to P_MDAC+P_C, and the P_MDAC stands for the power of MDAC in all stages, P_C stands for the power of all comparators.

Taking the channel noise of switches and opamp into consideration, one architectural approach to maximize the signal-to-noise ratio (SNR) with a given power budget is to determine an optimum way of choosing per-stage resolution and reduce sampling capacitor sizes along the pipeline^[19]. To simplify the analysis, the per-stage resolution n is assumed to be constant. The unit sampling capacitor of ith stage is $\gamma_{i}C_{\rm u}$ , where C_u is the unit capacitor of the first stage and $\gamma _{i}({\gamma =2}^{-nx})$ is the scaling factor of the ith stage. The x is taper factor. The speed factor η here varies between 0 and 1. The total input-referred noise is given by:

$\begin{align} & \sum\limits_{i=1}^{\infty }{{{N}_{i}}}=\frac{kT}{{{2}^{n}}{{C}_{\text{u}}}}+\frac{kT}{5{{C}_{\text{u}}}}\left( \frac{1}{{{4}^{n}}\gamma -1} \right) \\ & \times \frac{\left( 1+\eta \right)\cdot {{2}^{n}}\gamma \cdot 5{{N}_{\text{op}}}}{1-\frac{1}{\left( 1+\eta \right){{2}^{n}}+\eta \cdot {{2}^{n}}+{{2}^{n}}\gamma }+{{2}^{n}}\gamma +\frac{1}{{{2}^{n}}}}. \\ \end{align}$

(8)

where N_op = 2/3 holds for long-channel devices. Nonetheless, N_op can be substantially larger than 2/3 if the noise model for short-channel devices is used. In addition, the current source and the cascode devices also contribute noise. In this analysis, N_op = 3 is assumed. In addition, the total conversion power can be derived as:

$P\propto \text{SNR}\cdot kT\cdot {{f}_{\text{s}}}\cdot \left( \frac{{{V}_{\text{gs}}}-{{V}_{\text{th}}}}{{{V}_{\text{dd}}}} \right)\cdot g\left( n, \gamma , \eta \right).$

(9)

$\begin{align} & g\left( n, \gamma , \eta \right)=\left( \frac{1+\eta }{1-\gamma } \right)\left( {{2}^{n}}-\frac{1}{1+\eta }+\eta \cdot {{4}^{n}}+{{4}^{n}}\gamma \right) \\ & \times \{\frac{1}{{{2}^{n}}}+\frac{\frac{1}{5}}{{{4}^{n}}\gamma -1} \\ & \times [\frac{\left( 1+\eta \right)\cdot {{4}^{n}}\gamma \cdot 5{{N}_{\text{OP}}}}{{{2}^{n}}-\frac{1}{1+\eta }+\eta \cdot {{4}^{n}}+{{4}^{n}}\gamma }+{{2}^{n}}\gamma +\frac{1}{{{2}^{n}}}]\}. \\ \end{align}$

(10)

where f_s is the sampling rate, V_gs -V_th is the overdrive voltage of the amplifier input transistor, and V_dd is the supply voltage. Since the ADC adopted in CCD AFE operates at 40 MHz, the speed factor η=0.5. In Figure 6 (a), g(n, γ, η) is plotted against x for n=1, ..., 5 to make the power optimization analysis. The plot indicates that a 2-3 b/s architecture is optimum for the system design. The scaling factor γ=0.189 when n=2, and γ=0.083 for n=3.

In addition, for high-resolution ADC with intermediate or high conversion speed, the comparator with pre-amplifier consumes more power. So it is important to obtain lower power from comparators through optimizing the per-stage resolution and quantity of stages. Since all comparators are same, the total power of comparators is proportional to numbers of comparators. Pipeline ADC with redundancy calibration has one bit more in each stage except the last flash stage. So when the total quantization precision is n bits, and the number of quantization stage is k, comparators in ith stage is, 2^b_i+1-2, i=1, 2, ..., k-1, where b_i is the resolution.

In addition, the last flash conversion stage has comparators of 2^b_k-1. The resolution n of ADC is equal to. Thus, the total number m of comparators in ADC is equal to. According to Cauchy theory, it is obtained as follows:

$mk\cdot {{2}^{n/k}}-2k+1.$

(11)

So when the resolution n and number of conversion stages k are certain in ADC, the minimum value of m can be obtained. Assuming η=kb+c, it can be obtained as follows:

${{m}_{\min }}=c\cdot {{2}^{b+1}}+(k-c){{2}^{b}}-2k+1.$

(12)

It is well known that the minimum value m could be obtained when the ADC consisted of k-c stages with b bits and c stages with b+1 bits. Thus the power consumed by comparators is lowest. Through analyzing, in a 14-bit ADC, when k=7, c=6, b=2, the minimum number of comparators b=2. Combined with power optimizing analysis above, it indicates that 2 b/s architecture is the optimum for the system design. In other words, the system power is lower when the ADC has seven conversion stages, and the resolution of the front six stages is 2 bits.

Normally, the distribution of resolution per stage is chosen mainly based on the consideration of noise and power. But in the real situation, the linearity of ADC, such as differential non-linearity (DNL), is very important. DNL is a direct result of the capacitance mismatch error caused by the manufacturing process. Because of the accumulative inter-stage gain, the later stages contribute a smaller error. Thus the error introduced by the first stage is most serious. The DNL introduced by the first stage is given as follows:

$DNL\propto \frac{{{2}^{N-{{b}_{1}}/2\text{ }}}}{\sqrt{{{C}_{\text{total}}}}},$

(13)

where C_total is the total capacitance of the digital-to-analog sub-converter array, N is the resolution of the converter, and b₁ is the resolution of the first stage. As a result, DNL improves by a factor of with every extra bit of resolution in the first stage. Meanwhile, for an N-bit resolution, the deviation of capacitance should satisfy the following equation.

$\Delta \frac{1}{{{2}^{N-{{b}_{1}}+1}}},$

(14)

where Δ is the standard deviation of capacitance mismatch, which is proportional to the reciprocal of capacitance area. The fitted curve of capacitor mismatch Δ versus 1/Area is shown in Figure 6(b). In SMIC 0.18 μm process, for MIM capacitance, the proportionality coefficient slope between Δ and 1/Area is equal to 64.6. The unit capacitance of MIM is 0.971 fF/μm². Therefore, when the resolution of the first stage is 2 bit/s, the area of unit sampling capacitance should be 5292 μm² to satisfy the demand of capacitance mismatch error. The cost of area is very large. So taking the chip area and DNL into consideration, it is meaningful to increase by an extra one effective bit of the first stage. When the resolution of the first stage is 3 bit/s, the area of capacitance in the first stage is equal to 2646 μm². So the improvement is obvious. Therefore, it is meaningful to choose 3 bit/s as the resolution of the first stage with the consideration of DNL and power.

In addition, because of the adjustment in the resolution of the first stage, it is necessary to determine the scaling factor γ₁ between the first stage and the second stage again. The input referred noise of the first stage is given as follows:

$\overline{V_{\text{in}, \text{n}}^{2}}=\frac{1}{A_{1}^{2}}\frac{{{N}_{\text{op}}}KT}{\beta {{C}_{\text{1L}}}}.$

(15)

where A₁ is the gain of the first stage, C_1L is the load capacitance in the output node, and β is the feedback factor. So the total input referred noise is given as follows.

where n (n=2) is the resolution per stage from the second stage, $\gamma(\gamma =0.189)$ is the scaling factor from the second stage, and C₂ is the unit capacitance of the second stage. Assuming $C_{2}=\lambda C_{1}$ , λ is the scaling factor between the first stage and second stage. Through careful analysis, λ=0.35. Finally, the topology of ADC is determined and shown in Figure 1.

Since the input of ADC is obtained from the CDS directly, the input signal may exceed the input range of ADC. We further optimize the first stage using out-of-range detection to monitor whether the swing of input signal exceeds the input range. After redundancy digital calibration, if the highest bit for out-of-range detection is 0, it indicated that input signal does not exceed the dynamic range of ADC; in contrast, if the highest bit is 1, the input signal exceeds the range. So through the detection of the digital code from ADC, we can modify the gain of CDS through controlling register to regulate the capacitance array. Through this operation, we can avoid the input of ADC exceeding the range. The cost of this design is two more comparators in the first stage, but the integrality for processing CCD signal is guaranteed.

3. Programmable, high-precision timing core

A high-precision, programmable timing core is very important for CCD arrays and CCD analog front end. The timing core will provide clocks including reset gate signal RG, horizontal driving clock H1-H4 and correlated double sampling clocks SHP/SHD. As shown in Figure 7, the timing core proposed in this paper contains the delay lock loop (DLL), clock selector circuit and clock assembling circuit.

The high-precision programmable timing core utilizes the master clock CLI, which has the same period as the CCD pixel period, as the reference clock signal. The CLI signal is generated by the image processor or crystal oscillator outside. As shown in Figure 7, the DLL divides one pixel period into 48 parts. The adjacent clock P[i] and P[i+1] have a delay of T_CLI/48. The DLL contains the phase detector (PD), charge pump (CP), voltage-controlled delay line (VCDL) and buffer. VCDL consists of 48 delay cells with the same structure. Every delay cell generates one phase clock signal via output buffer, from P^[1] to P[48]. The reference clock CLI generates the clock P[0] through the same buffer. The PD detected CLK_REF and CLK_OUT with P[0] and P[48] as input signal. After the whole loop locked, the signal CLK_REF and CLK_OUT have the same phase.

Assume that T_cell(i) is the delay time of the ith delay cell, B(i) is the delay time of the ith output buffer, and N (N=48) is the number of delay cells. Ideally, when DLL achieves locking state, the timing relationships among the output buffers corresponding to different delay cells should be satisfied with the following two equations:

$\sum\limits_{i=1}^{N}{{{T}_{\text{cell}}}(i)}+B(N)-B(0)={{T}_{\text{CLI}}},$

(16)

and

${{T}_{\text{cell}}}(i)+B(i)-B(i-1)=\frac{{{T}_{CLI}}}{N}, \quad i=1, 2, \cdot \cdot \cdot , N.$

(17)

According to the above equations, the phase spacing in the buffers and delay cells would be equal if there is no mismatch existing among delay cells and output buffers. Unfortunately, in practice, each delay cell or output buffer may introduce a different delay time due to device mismatch or wiring mismatch. The equal phase spacing at outputs is impossible without any calibration mechanism. In the situation that the master clock is 40 MHz, the delay time T_CLI/48 is 520 ps ideally. Figure 8 shows 1000 runs of Monte-Carlo simulation results for static timing errors among 48 delay cells, where the device mismatch and process variation are added. In SMIC 0.18 μm CMOS technology, the process and mismatch will cause the delay time with mean value μ of 519.49 ps and standard deviation σ of 19.38 ps, yielding $\sigma /\mu =3.7%$ . Assuming CCD input signal is constant when sampled by the AFE, the error induced by mismatch and process variation would not generate any degradation in dynamic performance of AFE.

The timing core proposed in this paper can be programmed by control registers which are written by serial interference outside. The registers control the clock selector to select the corresponding clock from P^[1] to P[48]. Combining Figure 7 and Figure 9 together, it is known that that the clock selector and clock combiner are needed to work together to generate the corresponding clock. In Figure 7, the 48 phase clock signals from DLL are connected to two multiplexers in the clock selector circuit. The multiplexers, controlled by clock selector register signals SELx[5:0] and SELy[5:0], select two clock signals as PSELx and PSELy from 48 phase clocks. Then these two clock signals were combined to get final signal CLK_IN through the clock assembling circuit. The topology structure of clock assembling circuit which contains multiplexers is shown in Figure 9, and the circuit is separated into three groups. The first group contains twelve four-to-one multiplexers, and the second group and third group contain four and one four-to-one multiplexer, respectively. Every group has two bits control signal from the clock control register. The control signal of the first group is corresponding to SELx[1:0]. In the same way, the second and third group are corresponding to SELx[3:2] and SELx[5:4], respectively. Under the control of the clock selector, the multiplexer can select a clock as PSELx from 48 clock signals out of DLL.

The clock signal P_SELx and P_SELy selected by clock selector are connected to the clock-assembling circuit to generate the output clock. The whole clock-assembling circuit contains four clock-assembling cells to generate key timing signals for the CCD and AFE. Figure 9 shows the structure of a clock-assembling cell. The whole clock-assembling circuit forms a feedback loop. The input signal P_SELx connects to the gates of M0 and M6, and P_SELy connects to the gates of M1 and M7. The signalsc and control the gates of M2, M5 and M3, M4 respectively. The signal c is opposite to. The drains of M2, M3, M4 and M5 connect together, and control the flipping of output clock signal of D flip-flop through the voltage in node A.

The principle of clock assembling is following: Assuming the output clock CLK_IN is low in the beginning, so the voltage of node B is high. For the two-to-one multiplexer, when the input sel is equal to zero, the output equals to 1. When sel is equal to one, the output equals 0. So the voltage of c is low and the voltage of is high. As a result, M5 and M3 turn on, and M2 and M4 turn off. When input signal P_SELy changes from low level into high level, the voltage in the node A turns from high level to low level. Thus the D flip-flop gets the new data from the input under the trigger clock signal. Since the voltage of node B is high, the CLK_IN turns from the low level to high level. Therefore the rising edge of P_SELy determines the rising edge of CLK_IN. In the same theory, the falling edge of CLK_IN is determined by the rising edge of P_SELx. As a result, the timing of CLK_IN can be controlled by modulating P_SELx and P_SELy. In other words, through selecting the different phase clock from P^[1] to P[48] as P_SELx and P_SELy, the timing of the special clock can be modulated.

The output clocks of proposed AFE connect to the programmable drive-strength circuit which consists of seven clock driving cells. Under the control of 3-bits control register, the user can select the number of the clock driving cells to get eight modes for different driving currents in different clock load applications. The simulation results are shown in Figure 10. The modes provided in the AFE include 6.2, 12.4, 18.6, 24.8, 31, 37.2, 43.4 mA and off mode.

4. Measurement results

The prototype of CCD analog front end was implemented in SMIC 0.18 μm CMOS process. The chip photo of proposed AFE is shown in Figure 11, with an active area of 2.8 × 4.8 mm². When the frequency of input signal is 6.069 MHz and the sampling frequency is 40 MHz, the measurement result of the dynamic performance of the proposed CCD AFE is shown in Figure 12. The signal to noise and distortion (SNDR) is 70.3 dB; the effective number of bits is 11.39 bit. The above measurement results are obtained under the condition that the AFE has a full scale input signal, and programmable gains of VGA and CDS is 0 dB at the same time. From the results shown above, the AFE described in this paper has a very excellent dynamic performance.

The measurement results for the output clocks H1 and RG of the proposed AFE at 8 MHz are shown in Figure 13(a). The measurement results indicate that the clocks generated by the AFE have good performance in period and duty cycle. The measured RMS jitters for 40 MHz output clock is shown in Figure 13(b). The Jitter_RMS is 65.554 ps under 20000 samples. Since the CCD input signal is constant when sampled by the SHD/SHP clock, the dynamic performance of AFE will not be influenced. Thus the performance of the timing core can satisfy the application very well. The figure test of the proposed AFE is provided in Figure 14. Figure 14(b) is the transformed image from the CCD AFE, compared to the original image shown in Figure 14(a). It is observed that the CCD AFE has an excellent performance.

According to the measurement results, the CCD AFE described in this paper has an obvious advantage in comparison with the previous circuits present in the papers. The performance comparison of analog front end is shown is Table 2. It is observed that the proposed CCD AFE has the competitive performance in power and static performance. Moreover, it is more advantageous in speed, resolution and dynamic range. For example, compared with references^[12-15], the proposed work has obvious advantages in convention speed. In addition, the proposed work provides wider programmable gain range and more flexible programmable clock function. Therefore the circuit described here can satisfy requirements of video application extensively and flexibly, avoiding the waste in cost and area caused by other auxiliary chips.

5. Conclusion

A high-precision 14-bit 40MHz CCD AFE with LVDS output is presented in this paper. It consists of a digitally controlled wideband VGA, CDS, a pipelined ADC using power optimization, a high-precision timing core with programmable timing and drive-strength. Compared with conventional AFEs, the system integrated all key parts for processing the CCD analog signal. This work achieves a 14-bit resolution with excellent performance. The proposed AFE can be applied in extensive fields, especially in the high-speed and high-precision field. The measured results indicate the proposed CCD AFE have an excellent performance in the applications.