1. Introduction

With the exploding growth of the wireless communication markets, a mobile terminal needs to be able to support multiple standards. Thus, multimode transceivers, software-defined radio (SDR), and cognitive radios have attracted a great deal of interest in both academic and industry researches^[1–4]. SDR is considered to be one of the most important sections for future communication systems, because of its reconfiguration and multimode operation features. Two key building blocks in SDR hardware are the reconfigurable digital baseband and the wideband radio frequency (RF) front-end^[5]. In the multimode receivers, the use of a broadband front-end is more attractive in low-cost system-on-chip (SoC) design due to its lower magnetic mutual coupling and smaller chip area. However, it is a technical challenge to design a wideband RF front-end.

The super heterodyne architecture used in most mobile terminals is not suitable for wideband RF front-end application, since the image rejection filters and intermediate frequency (IF) channel filters cannot be programmed. The direct conversion architecture is a better candidate for broadband terminals. Because terminals using this architecture do not need components such as image-reject filters, allowing a higher level of integration^[6]. The fast-evolving CMOS technologies make it possible for a broadband RF front-end to cover the frequencies ranging from several megahertz to several gigahertz. Hence, CMOS technology is an appropriate process for wideband RF front-end implementation^[1].

In this paper, a self-biased resistive-feedback LNA is proposed, which combines shunt-peaking inductors and a gate inductor to extend the bandwidth. Based on the proposed LNA, a 0.7–7 GHz wideband RF front-end is implemented. The wideband receiver RF front-end can be applied to point to point communication systems and femtocell/picocell/microcell base stations, as well as general-purpose radio systems. The paper is organized as follows. After an introduction in Section 1, Section 2 provides a brief review of wideband LNA. Section 3 shows the implementation of the voltage-driven passive mixer and IF amplifier. Section 4 reports the measurement results of the front-end SoC. Finally, Section 5 concludes this paper.

2. Wideband LNA

The LNA is the first active block in the receiver and is essential for the whole system^[7]. In this section, the proposed LNA based on resistive feedback will be discussed in detail with the focus on input impedance matching, amplifier gain and NF.

Fig. 1 shows the simplified schematic of the proposed three-stage wideband LNA. In the first stage, the feedback resistor is implemented directly between the drain of the input transistor M₁ and the input node, which can ensure no bandwidth degradation and need no additional bias circuits. A PMOSFET M₂ is chosen as the load so that the gate voltage of M₁ and M₃ can be adjusted to obtain high voltage gain over a wide range of frequencies, and it can also counteract the influence of process variation. In the second stage, the common-source amplifier is added to improve the isolation between the input and the output. The shunt peaking inductor is also used in the second stage to further enhance the bandwidth. The common-source buffer with a shunt peaking inductor is employed as the third stage to achieve wideband output matching. The signal at the former stage is directly coupled to the next stage to ensure no extra power consumption and less bandwidth degradation.

2.1 Voltage gain and bandwidth enhancement

To increase the bandwidth of the LNA, a number of methods are adopted in this design. Firstly, the feedback resistor R_f is connected between the drain of the input transistor and the input node, which can reduce the input quality factor (Q) and thus extend the bandwidth. Secondly, an inductor L_g placed inside the feedback loop at the gate of the input transistor is added. According to reference^[8], the inductor L_g will introduce three poles in the transfer function of the voltage gain. Thirdly, the inductor shunt peaking technique has been used. The simulation result shows that the shunt peaking inductor can increase the bandwidth by 19% compared with that of no shunt peaking inductors^[9]. Finally, the inductor at the drain of the input transistor is added, which can counteract some capacitance of the next stage at high frequency and increase the flexibility of the input matching.

The overall gain can be expressed as ${A_{\rm v}}(s) = {A_{\rm v1}}(s) \cdot$ ${A_{\rm v2}}(s) {A_{\rm v3}}(s)$ and the gain of each stage is listed below:

$${A_{{\rm{v1}}}}(s) = (1 - \frac{{{g_{{\rm{m}}1}}{R_{\rm{f}}}}}{{{s^2}{C_{{\rm{gs}}1}}{L_{\rm{g}}} + 1}}) \frac{1}{{1 + {R_{\rm{f}}}{Y_{\rm{L}}}(s)}} \frac{{{g_{{\rm{m}}2}}{r_{{\rm{ds}}2}}{L_{{\rm{s}}2}}}}{{{g_{{\rm{m}}2}}{r_{{\rm{ds}}2}}{L_{{\rm{s}}2}} + {L_{{\rm{d}}1}}}},$$

(1)

$${A_{{\rm{v}}2}}(s) = {g_{{\rm{m}}3}} \frac{{{R_{{\rm{d}}3}} + s{L_{{\rm{d}}3}}}}{{{s^2}{L_{{\rm{d}}3}}{C_{{\rm{gs}}4}} + s{R_{{\rm{d}}3}}{C_{{\rm{gs}}4}} + 1}},$$

(2)

$${A_{{\rm{v}}3}}(s) = {g_{{\rm{m}}4}} [({R_{{\rm{d}}4}} + s{L_{{\rm{d}}4}})//50\Omega ],$$

(3)

where the Y_L(s) represents the load admittance at the drain of the M₁, and can be expressed as:

$${Y_{\rm{L}}}(s) = \frac{{({s^2}{g_{{\rm{m}}2}}{r_{{\rm{ds}}2}}{L_{{\rm{s}}2}}{C_{\rm{L}}} + 1)(s{L_{{\rm{d}}1}} + {r_{{\rm{ds}}1}}) + s{g_{{\rm{m}}2}}{r_{{\rm{ds}}2}}{L_{{\rm{s}}2}}}}{{{r_{{\rm{ds}}1}}[s{L_{{\rm{d}}1}}({s^2}{g_{{\rm{m}}2}}{r_{{\rm{ds}}2}}{L_{{\rm{s}}2}}{C_{\rm{L}}} + 1) + s{g_{{\rm{m}}2}}{r_{{\rm{ds}}2}}{L_{{\rm{s}}2}}]}}.$$

(4)

Here, the C_L represents the load capacitor of the first stage and C_L = C_gs3 + C_db2.

2.2 Input impedance matching

Input impedance matching is an important parameter in LNA design because poor matching at the receiver input will lead to significant reflections, an uncharacterized loss, and possibly voltage attenuation. In the proposed LNA, the wideband input matching is achieved by adjusting the first stage gain, the feedback resistor, the inductor at the gate of M₁ and an inductor in series at the drain of the M₁.

Fig. 2 shows the small signal equivalent circuit of the input network, where the capacitor C_pad represents the parasite capacitor of the input pad. The input admittance can be derived as:

$$\begin{split}{Y_{{\rm{in}}}}(s) =& s{C_{{\rm{pad}}}} + \frac{{s{C_{{\rm{gs}}1}}}}{{{s^2}{L_{\rm{g}}}{C_{{\rm{gs}}1}} + 1}} \\& + {g_{{\rm{m}}1}} \frac{1}{{{R_{\rm{f}}}}} \frac{1}{{({s^2}{L_{\rm{g}}}{C_{{\rm{gs}}1}} + 1) {Y_{\rm{L}}}(s)}}.\end{split}$$

(5)

The Y_L(s) is given in Eq. (4).

2.3 Noise analysis

The noise performance of the proposed LNA is mainly determined by the first stage according to the Friis’ equation. In the first stage, three primary noise sources are the noise of the input transistor M₁, the noise of the loading device M₂, and the noise of the feedback resistor. The noise contributed by M₁ can be optimized by selecting an appropriate width. When it comes to the noise of M₂, the shunt peaking inductor plays the role of source degeneration, which could suppress the noise of M₂ at high frequencies. The noise factor is shown in Eq. (6).

$$F \approx 1{\rm{ + }}\frac{{{R_{\rm{s}}}}}{{{R_{\rm{f}}}}} + \frac{{{\gamma _1}(1 + {\omega ^2}C_{{\rm{gs}}}^2R_{\rm{s}}^2)}}{{{\alpha _1}{g_{{\rm{m}}1}}{R_{\rm{s}}}}} + \frac{{{\gamma _2}{g_{{\rm{do}}2}}(1 + {\omega ^2}C_{{\rm{gs}}}^2R_{\rm{s}}^2)}}{{g_{{\rm{m}}1}^2{R_{\rm{s}}}(1 + {\omega ^2}L_{{\rm{s}}2}^2g_{{\rm{m}}2}^2)}}.$$

(6)

3. Voltage-driven I/Q passive mixer

The passive mixer has the great benefits of low flicker noise and high linearity with low power consumption. Therefore, it is adopted here to mitigate design tradeoff between low-frequency flicker noise and various IF bandwidth requirements.

As shown in Fig. 3, the proposed mixer is composed of passive switches and IF amplifiers. The passive switches, as biased in the on-overlap region for linearity performance, are driven by the local oscillator (LO) chains. The size of the passive switches needs to be selected properly, because the white noise of the mixer depends on the channel resistance of the MOSFET, which are on at a given time. The IF amplifier can not only provide suitable gain to compensate the loss in the passive mixer but also filter the high frequency signal.

The differential conversion gain of I/Q output is given by

$${A_{{\rm{conversion}}}} = \frac{2}{\pi } {g_{{\rm{m}}10}} ({r_{{\rm{ds}}12}}//{R_5}).$$

(7)

Here, the parameters of the RF transistors and resistors satisfy g_m10 = g_m11 = g_m15 = g_m16, r_ds12 = r_ds13 = r_ds17 = r_ds18, and R₅ = R₆ = R₇ = R₈.

In the LO chain, as shown in Fig. 4, a divide-by-2 divider is used to generate the quadrature signal. After the divider, the LO signal is distributed to a three-stage buffer chain. The chain includes two cascade differential amplifiers as the first two stages and inverter-type drivers as the third stage for maximal signal swing.

4. Wideband RF front-end implementation and measurement results

Based on the broadband LNA and voltage-driven passive mixer mentioned above, the broadband RF receiver front-end chip was fabricated in CMOS process, as shown in Fig. 5. It occupies an area of 1.67 × 1.08 mm², including pads and guard rings. The chip is mounted on a printed circuit board (PCB) with chip-on-board technique for measurement.

The measured and simulated results are given below. The measured results introduce some loss due to the bonding. Fig. 6 presents the measurement result of S₁₁ from 0.5 to 8.5 GHz. The measured S₁₁ is better than −10 dB from 700 MHz to 7 GHz and reaches the best input impedance matching of −20 dB at about 6.8 GHz.

As depicted in Fig. 7, NF is less than 3.5 dB when the IF frequency is from 10 to 600 MHz and achieves a minimum value of 3.2 dB at 70 MHz when the LO is 2.5 GHz. In Fig. 8, the conversion gain is given. The maximum conversion gain reaches 26 dB and the IF 3 dB-bandwidth is larger than 500 MHz. This chip is reconfigurable from 0.7 to 7 GHz. The conversion gain under different LO frequencies is shown in Fig. 9.

Table 1 lists the major specifications of various wireless communication standards along with the performances of this work. The performance summary and the comparison with recently published results are listed in Table 2. According to Table 2, this work achieves wider RF and IF bandwidths and lower noise.

5. Conclusion

In this paper, the design and measurement results of a wideband receiver front-end SoC in CMOS technology have been presented. The proposed single-ended LNA adopts a shunt-peaking technique to boost the bandwidth, resulting in excellent overall performances throughout the spectrum ranging from 0.7 to 7 GHz. Based on this resistive-feedback broadband LNA, the wideband RF receiver front-end SoC can cover multiple communication applications. Experimental results validate that the wideband receiver RF front-end achieves good input impedance matching, high gain, low noise and wide IF bandwidth.