Chin. J. Semicond. > 2007, Volume 28 > Issue 4 > 542-548

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Key Techniques of Frequency Synthesizer for WLAN Receivers

Tang Lu, Wang Zhigong, Xu Yong and Li Zhiqun

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Abstract: Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied.Its structure is analyzed and the main parameters are proposed.A monolithic LC-tuned voltage controlled oscillator (LC-VCO) with low phase noise is fabricated with TSMC 0.18μm RF (radio frequency) CMOS technology.The measured phase noise is -117dBc/Hz at 4MHz off the center frequency of 4.189GHz.A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process.The measured results show that the IC can work well under a 1.8V power supply.Its total power dissipation is only 13mW.

Key words: PLLWLANVCOdown scaling

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    Received: 18 August 2015 Revised: 11 December 2006 Online: Published: 01 April 2007

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      Tang Lu, Wang Zhigong, Xu Yong, Li Zhiqun. Key Techniques of Frequency Synthesizer for WLAN Receivers[J]. Journal of Semiconductors, 2007, 28(4): 542-548. ****Tang L, Wang Z G, Xu Y, Li Z Q. Key Techniques of Frequency Synthesizer for WLAN Receivers[J]. Chin. J. Semicond., 2007, 28(4): 542.
      Citation:
      Tang Lu, Wang Zhigong, Xu Yong, Li Zhiqun. Key Techniques of Frequency Synthesizer for WLAN Receivers[J]. Journal of Semiconductors, 2007, 28(4): 542-548. ****
      Tang L, Wang Z G, Xu Y, Li Z Q. Key Techniques of Frequency Synthesizer for WLAN Receivers[J]. Chin. J. Semicond., 2007, 28(4): 542.

      Key Techniques of Frequency Synthesizer for WLAN Receivers

      • Received Date: 2015-08-18
      • Accepted Date: 2006-10-08
      • Revised Date: 2006-12-11
      • Published Date: 2007-04-09

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