| Citation: |
Sui Xiaohong, Liu Jinbin, Gu Ming, Pei Weihua, Chen Hongda. Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings[J]. Journal of Semiconductors, 2005, 26(12): 2275-2280.
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Sui X H, Liu J B, Gu M, Pei W H, Chen H D. Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings[J]. Chin. J. Semicond., 2005, 26(12): 2275.
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Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings
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Abstract
A monolithic integrated CMOS preamplifier is presented for neural recording applications.Two AC-coupled capacitors are used to eliminate the large and random DC offsets existing in the electrode-electrolyte interface.Diode-connected nMOS transistors with a negative voltage between the gate and source are candidates for the large resistors necessary for the preamplifier.A novel analysis is given to determine the noise power spectral density.Simulation results show that the two-stage CMOS preamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 38.8dB,a DC gain of 0,and an input-referred noise of 277nVrms integrated from 0.1Hz to 1kHz.The preamplifier can eliminate the DC offset voltage and has low input-referred noise by novel circuit configuration and theoretical analysis.-
Keywords:
- preamplifier,
- DC offset,
- input-referred noise
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References
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Proportional views
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