| Citation: |
Zhu Haobo, Mao Luhong, Yu Changliang, Ma Liyuan. Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver[J]. Journal of Semiconductors, 2007, 28(5): 676-680.
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Zhu H B, Mao L H, Yu C L, Ma L Y. Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver[J]. Chin. J. Semicond., 2007, 28(5): 676.
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Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver
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Abstract
A sensitivity design method for a CMOS optoelectronic integrated circuit (OEIC) receiver is reported.The receiver consists of a regulated cascade (RGC) transimpedance amplifier (TIA) and a double photodiode (DPD) detector.The noise and sensitivity of the receiver are analyzed in detail.The noise mainly comes from the thermal noise of resistors and the flicker noise of MOSFETs.The relationship between noise and receiver sensitivity is presented.The sensitivity design method for the receiver is given by a set of equations.The OEIC receiver was implemented in a CSMC 0.6μm standard CMOS process.The measured eye diagram shows that the CMOS OEIC receiver is able to work at bit rates of up to 1.25GB/s and the sensitivity is -12dBm.-
Keywords:
- CMOS,
- OEIC,
- receiver,
- sensitivity,
- noise
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References
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Proportional views
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