In order to clarify the effect of Pt addition on the stress of NiSi film,in situ stress measurements were taken to evaluate the stress evolution during heating and cooling treatment of Ni1-xPtxSi alloy films with different Pt concentrations.The room temperature stress,which is mainly thermal stress,was measured to be 775MPa and 1.31GPa for pure NiSi and pure PtSi films grown on Si (100) substrates,respectively.For Ni1-xPtxSi alloy film,the room temperature stress was observed to increase steadily with Pt concentration.From the temperature dependent stress evolution curves,the stress relaxation temperature was found to increase from 440℃ (for pure NiSi film) to 620℃ (for pure PtSi film) with increasing Pt concentration,thus influencing the residual stress at room temperature.

The nonlinear optical properties of Al-doped nc-Si-SiO2 composite films have been investigated using the time-resolved four-wave mixing technique with a femtosecond laser.The off-resonant third-order nonlinear susceptibility is observed to be 1.0e-10 esu at 800nm.The relaxation time of the optical nonlinearity in the films is as short as 60fs.The optical nonlinearity is enhanced due to the quantum confinement of electrons in Si nanocrystals embedded in the SiO2 films.The enhanced optical nonlinearity does not originate from Al dopant because there are no Al clusters in the films.

High-power ridge-waveguide tapered InGaAs-AlGaAs lasers emitting at 980nm were fabricated.Lasers with a total length L=1850μm and different lengths of the ridge waveguide Lrw were processed to study the influence of the straight section on the spatial mode filtering.When Lrw is 450μm,the devices have the optimized maximum output power and beam quality,and the output power P is 4.28W.The beam propagation ratio M2 is 3.79 at 1W.

A stereo 15bit delta-sigma digital-analog converter (ΔΣ DAC) integrated with a filterless class D power amplifier is introduced.It consumes no static power,and its maximum output power is 436mW with an 8Ω load.Its output dynamic range exceeds 100dB.The circuit is implemented with a TSMC 0.18μm process.The die area is 0.28mm2.The supply voltage is 1.8V for the digital part and 3.3V for class D.

A new FM transmitter is reported.It adopts a fractional-N PLL synthesizer to realize the FM modulator.An extra offset current has also been applied to eliminate the effects of the mismatch in CP.The chip is fabricated with CSMC 0.5μm DPTM CMOS technology.Experiments show that it achieves THD≤0.08% and SNR≥82dB,and the maximum outband emission energy ≤-90dBc/Hz.Furthermore,it also uses an auto frequency adjusting method to avoid tuning up the external inductances.All these merits are very suitable for FM transmission.

Ferromagnetic MnSb films were synthesized on Si wafers by physical vapor deposition.X-ray diffraction revealed that the films primarily consisted of MnSb alloy.Nanorods and nanoleaves were observed in the MnSb films by field-emission scanning electron microscopy.These nanorods had an average diameter of 20nm and a length of up to hundreds of nanometers.The nanoleaves had a width and thickness of about 100 and 20nm,respectively.Magnetic hysteresis loops were measured by an alternative gradient magnetometer,and the loops showed strong geometrical anisotropy.

We investigate the negative bias temperature instability (NBTI) of 90nm pMOSFETs under various temperatures and stress gate voltages (Vg).We also study models of the time (t),temperature (T),and stress Vg dependence of 90nm pMOSFETs NBTI degradation.The time model and temperature model are similar to previous studies,with small difference in the key coefficients.A power-law model is found to hold for Vg,which is different from the conventional exponential Vg model.The new model is more predictive than the exponential model when taking lower stress Vg into account.

An RF bandpass filter with a Q-enhancement active inductor is presented.The design technique for a tunable Q-enhancement CMOS active inductor operating in the wide RF-band is described.Moreover,issues related to noise and stability of the active inductor are explained.The filter was fabricated in 018μm CMOS technology,and the circuit occupied an active area of only 150μm×200μm.Measurement results show that the filter centered at 2.44GHz with about 60MHz bandwidth (3dB) is tunable in center frequency from about 2.07 to 2.44GHz.The 1dB compression point is -15dBm while consuming 10.8mW of DC power,and a maximum quality factor of 103 is attained at the center frequency of 2.07GHz.

A sensitivity design method for a CMOS optoelectronic integrated circuit (OEIC) receiver is reported.The receiver consists of a regulated cascade (RGC) transimpedance amplifier (TIA) and a double photodiode (DPD) detector.The noise and sensitivity of the receiver are analyzed in detail.The noise mainly comes from the thermal noise of resistors and the flicker noise of MOSFETs.The relationship between noise and receiver sensitivity is presented.The sensitivity design method for the receiver is given by a set of equations.The OEIC receiver was implemented in a CSMC 0.6μm standard CMOS process.The measured eye diagram shows that the CMOS OEIC receiver is able to work at bit rates of up to 1.25GB/s and the sensitivity is -12dBm.

Based on the physical characteristics of SiGe material,a new three-dimensional (3D) CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of SixGe1-x material for pMOS.The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI.The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs.The delay time of the 3D Si-SiGe CMOS inverter is 2~3ps,which is shorter than that of the 3D Si-Si CMOS inverter.

This paper introduces a high-performance analog front end for a passive UHF RFID transponder IC,which is compatible with the ISO/IEC 18000-6B standard,operating at the 915MHz ISM band with a total supply current consumption less than 8μA.There are no external components,except for the antenna.The passive IC’s power supply is taken from the energy of the received RF electromagnetic field with the help of a Schottky diode rectifier.The RFID analog front end includes a local oscillator,clock generator,power on reset circuit,matching network and backscatter,rectifier,regulator,and AM demodulator.The IC,whose reading distance is more than 3m,is fabricated with a Chartered 0.35μm two-poly four-metal CMOS process with Schottky diodes and is EEPROM supported.The core size is 300μm×720μm.

A 2.5Gb/s/ch data recovery (DR) circuit is designed for an SFI-5 interface.To make the parallel data bit-synchronization and reduce the bit error rate (BER),a delay locked loop (DLL) is used to place the center of the data eye exactly at the rising edge of the data-sampling clock.A single channel DR circuit was fabricated in TSMC’s standard 0.18μm CMOS process.The chip area is 0.46mm2.With a 2³¹-1 pseudorandom bit sequence (PRBS) input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps.The sensitivity of the single channel DR is less than 20mV with 1e12 BER.

A method using first principles and pseudopotentials based on density functional theory is applied to calculate the geometric structure,the formation energy of impurities,and the electronic structure of ZnO doped with Ag.The calculations indicate that ZnO doped with Ag expands.Furthermore,Ag dopants prefer to occupy the substitutional Zn sites,and an Ag substitution at a Zn site behaves as a deep acceptor.Our results are in good agreement with other calculated and experimental results.

MgxZn1-xO thin films with x=0,0.11,0.28,0.44,0.51,and 0.65 were grown on (0001) sapphire substrates with plasma-assisted molecular beam epitaxy.X-ray diffraction measurement reveals that there is only one MgxZn1-xO (002) peak at 34.46~34.67° with increasing Mg content up to 0.28,indicating the formation of single-phase MgxZn1-xO films with hexagonal crystal structure.When xrises to 0.44,a phase separation of MgxZn1-xO occurs.When x equals 0.65,the ZnMgO transforms completely from wurtzite to cubic structure.The effects of phase structure transition on optical properties of MgxZn1-xO alloy films were investigated via room temperature photoluminescence and absorption spectra.

Single-phase n-type (AgIn)xPb1-2xTe compounds were synthesized using the melting reaction method.Influences of (AgIn) substituting for Pb on the constituent phases and thermoelectric properties of the (AgIn)xPb1-2xTe(x=0.01~0.05) were investigated.Results indicate that single phase compound is obtained when the (AgIn) substitution fraction x≤0.04.However,the second phase (AgInTe2) was observed in the sample withx=0.05.The Seebeck coefficient increases gradually with the increasing of the (AgIn) substitution fraction x,and the electrical conductivity of the compounds decreases with the increasing of x.Thermal conductivity decreases with the increasing of x.In all of the n-type (AgIn)xPb1-2xTe compounds,(AgIn)0.01Pb0.98Te compound has the greatest ZT value,reaching 1.1 at 800K.

A series of PZT ceramic targets are prepared by traditional solid-phase reactive sintering,and their phase composition is examined by X-ray diffraction.It is shown that the existence of excess PbO could greatly inhibit the decomposition of PbZrO3 as well as the formation of pyrochlore,thus stabilizing the perovskite phase.However,excess PbO would make the ceramic composition change locally,thereby degrading the uniformity of the ceramic targets.In addition,one sole ceramic target fabricated by traditional solid-phase sintering tends to be stratified,which could be improved by sintering several samples or adopting advanced sintering technology.

A CdS thin film filter is grown on quartz substrate using femtosecond pulsed laser deposition.The influence of the substrate temperature on the structural and optical characteristics of CdS thin films is systematically studied in the range of 100~600℃.The results show that the structural quality is excellent for the CdS thin film that was fabricated at the substrate temperature of 450℃.Optical transmission shows that the CdS thin films possess a steep absorption edge,resulting in a sharp transition between absorbed and transmitted wavelengths,which can be used as an optical filter.

In order to increase Voc and improve the spectral response of CdS/CdTe solar cells,thus increasing their efficiency,we bring forward a new tandem structure.The top cell consists of thinner CdS/CdTe layers,and the bottom cell structure of thicker CdS/CdTe layers.The total structure is Glass/SnO2/CdS/CdTe/CdS/CdTe/ZnTe:Cu/Ni.The structural properties of the tandem solar cells have been investigated,revealing its different layers and showing that it has Voc of 852mV,Jsc of 13mA/cm2,and FF of 55.2%.The spectral response of the cell is improved,and it is demonstrated to have an efficiency of 8.16% for 0.071cm2 cells.Compared to the ordinary monolayer CdS/CdTe solar cells,the CdS/CdTe tandem solar cells have important value for investigating how to improve CdS/CdTe solar cells’ photovoltaic performance.

We report the deposition and structural characterization of zinc sulfide (ZnS) thin films by chemical bath deposition (CBD) from a bath containing thiourea,ZnSO4,and ammonia in aqueous solution.The XRF and XRD analysis of as-deposited and annealed films show that the films have cubic ZnS structure with Zn(OH)2.Transmission measurements show that the optical transmittance is about 90% when the wavelength is over 500nm.The band gap (Eg) value of the deposited film is about 3.51eV.The effect of the ZnS buffer layer deposition time on device performance is studied.The result shows that the cell performance with a CBD-ZnS buffer layer deposited for 25~35min is best.The performance of CIGS solar cells with different buffer layers is compared.These results suggest that CBD-ZnS thin film can alternate CBD-CdS thin film as the buffer layer of CIGS solar cells.

A novel three-dimensional (3D) continuous cellular automata (CA) model is presented for the simulation of silicon bulk etching processes.More high-index planes such as (211),(311),(331),(411) planes have been successfully incorporated into the novel 3D continuous CA model to increase the simulation accuracy.Simulation results agree with experimental results,indicating that the simulation accuracy has been increased.This is useful for the research of silicon bulk etching process and micro-electro-mechanical system (MEMS) design.

AlAs/GaAs/InGaAs double barrier-single well structures are grown on semi-insulating GaAs substrates by molecular beam epitaxy.By improving on material growth design and process design,the maximum PVCR of the RTD has reached 2.4,and the density of the peak current has reached 36.8kA/cm2.The parameters and I-V characteristics of the RTD have been measured,and the effects of quantum well width and thickness of the cap layer on the RTD I-V characteristics are analyzed.

Using the forward alternating current (ac) small signal method to measure the capacitance-voltage characteristic of an LED, negative capacitance can be observed.We propose that this phenomenon is a surface phenomenon, and there is no real negative capacitance.We further propose that the capacitance of the p-n junction in an LED is equivalent to the variable capacitance in a certain range of forward voltage.By the corresponding analysis of variable capacitance to the alternating current small signal, we find that the variable capacitance for certain parameters can shift the phase of the current by π,leading to negative capacitance in measurement.Additionally, an expression for the negative capacitance in an LED that relates it to the rotational frequency is obtained for the first time.

This paper presents a method based on dual-gate-oxide-thickness assignment to reduce the total leakage power dissipation of SRAM in 45nm bulk technology.The proposed technique incurs neither area nor delay overhead and can improve the static noise margin.In addition,it results in a slight change in the SRAM design flow.Three novel SRAM cell configurations are proposed.Simulation results demonstrate that this technique can reduce the total leakage power dissipation of 32kb of SRAM with these configurations by more than 50%.

The total dose irradiation effects under different bias configurations for fully-depleted (FD) silicon on insulator (SOI) devices are investigated,especially the influence on device performance from radiation-induced trapped-charges.The simulation results show that distribution of the electrical field is strongly dependent on the bias configuration.Moreover,the generation of trapped-charges is related to the electrical field.The variation of the electrical field distribution leads to the variation of trapped-charge distribution,which in turn results in the variation of device performance.Among the three different bias configurations,the OFF state has the highest density of trapped-charges and corresponds to the largest drift of threshold-voltage and leakage current of the front-gate transistor.

A novel storage cell is proposed.Its structure is similar to Whitaker’s cell,but four transistors are added to avoid voltage degradation.SPICE simulation results show that its static current drops dramatically compared with Whitaker’s cell,and the write speed is equivalent to that of other cells.No upset occurs when Au ions with an LET of 94MeV/ (mg·cm2) impacts by DESSIS and SPICE mix simulation.

An X band InGaP/GaAs HBT single stage MMIC power amplifier is reported.The self-aligning InGaP/GaAs HBT process was used to fabricate the circuit.The PA circuit is biased at the class AB state.The small signal S parameter test shows that at 8~8.5GHz,the linear power gain is 8~9dB,VSWRin＜2,and VSWRout＜3.After optimizing the collector bias,the linear gain is improved to 9~10dB.Under an 8.5GHz CW signal power test with optimized loading conditions,the P1dB of the circuit is 29.4dBm,relevant power gain is 7.2dB,and relevant PAE is 42%.The Psat of the circuit is 30dBm.

A novel BCD structure with semi-insulation bonding SOI is proposed.It reliably integrates a high voltage power device,CMOS,and BJT into a monolithic circuit.Integrated VDMOS lengthways is a unique feature of this structure.It is a useful technique in applications of automotive electronics,radiation hardening,and strong electromagnetic pulses (EMP).The breakdown voltage of this BCD structure VDMOS is 160V,its on-resistance is 0.3Ω,and its specific on-resistance is 26mΩ·cm2.The breakdown voltages of npn,pMOS,and nMOS are 50,35,and 30V,respectively,and the npn current gain and cut-off frequency are 120 and 700MHz,respectively.

An equivalent circuit model of a laser array is established,and simulated processes are imposed on the model using PSPICE.The simulated and experimental results indicate that the ideality factor of the laser array is equal to that of its elements,and the current leakage and abnormal ideality factor variation of elements can result in the increase of the ideality factor of the laser array.We propose a new method to detect the ideality factor of a laser array element by using an electrical derivative test of the laser array,and we also propose the use of the ideality factor of a laser array as a screen to estimate the reliability the array.

The light intensity distribution and development processes during the preparation of two-dimensional patterned silicon substrates by holographic lithography are simulated.Different periods can be achieved by varying the wavelength and the angle between the sample surface and the laser beams.Large-area uniform two-dimensional sub-micrometer patterned n-type doped (100) silicon substrate has been fabricated by single exposure with a triple beam and wet chemical etching.The method is suitable for fabricating array patterns on large silicon substrates.

The structural and territorial design of PZT thin film micro-sensors is processed.Using MEMS processes and standard silicon-based IC,the key techniques and technical conditions are obtained for PZT thin film micro-cantilever beams based on silicon.At the same time,the preparation and micro-pattern etching techniques of PZT thin films are investigated by experiment.Finally,a PZT thin film micro-sensor is successfully etched and the experimental foundations are laid for the research and development of the system on a chip.

A new micro-silicon capacitive accelerometer with novel "8-beams/mass" structure was designed and fabricated by applying a micro-machining process to (111) silicon wafer.The proof mass of this accelerometer is supported by eight suspension beams located symmetrically on the top/bottom surface of a (111) silicon wafer.By using an extremely slow rate of Si (111) plane etching in anisotropic KOH,along with DRIE and other MEMS processes,the dimension of these beams can be accurately controlled,and the symmetry of the "8-beams/mass" structure can be achieved.The performance of the accelerometer is measured with a typical resonance frequency of 2.08kHz,quality factor of 21.4,and sensitivity of 93.7mV/g.

Two parameters, one called the unified stacking factor (USF) and the other called the circuit virtual stacking factor (VSF), are defined based on the relationship between the transistor stacking effect and the leakage current of standard cells.A VSF-based leakage power evaluation model is then developed and used for evaluating and reducing the leakage power of CMOS combinational circuits.Experiments show that the VSF model is not needed for Hspice simulation when evaluating leakage power.For ISCAS85 benchmark circuits, satisfactory leakage power reduction can be achieved, and the optimization speed can be accelerated greatly.

A low-noise,low-offset folded-cascode amplifier for micro-sensor applications is presented.Low 1/f noise and offset are achieved by employing a chopper and dynamic element matching.The input signal bandwidth and output swing are extended with the use of the low impedance node chopping technique and a low-voltage cascode mirror structure.The chip has been realized in 0.35μm 2P4M CMOS technology.The amplifier features an open-loop gain of 839dB and a GBW of 10MHz.The measured typical residual input offset is less than 93.7μV,and the equivalent input low frequency noise is 19.6nV/Hz at a chopping frequency of 100kHz and supply voltage of 3.3V.

A build-in power supply circuits IP core for TFT-LCD driver IC is designed using 0.25μm CMOS LV/MV/HV hybrid voltage process.It is composed by four sub-blocks such as LDO regulators,capacitor-switched charge-pump circuits,VCOM and Vgoff driving buffer circuits.Both power supply voltages for TFT-LCD driver IC and driving voltages for TFT-LCD panel can be provided by this IP core.The temperature coefficients of voltages generated by LDO regulators are less than 13.7ppm/℃.A new topology of charge pump which generates the highest voltage VGH and the lowest voltage VGL is proposed,and the settling time of VGH and VGL is reduced to less than 100ms.The voltages generated by VCOM and Vgoff driving buffer circuits can be adjusted by programmable register.All generated voltages are with their stable values in 200ms when power is on.The static power dissipation of this IP core is less than 2mW.

This paper reviews the development of bulk SiC single crystals grown by sublimation and summarizes their actual status.The thermal field and growth techniques for the growth of SiC crystal are introduced in this paper.The machining technology of large SiC single crystal is also introduced.With the aid of numerical simulation,we have continued to make efforts to optimize the crucible design and the crucible position in the growth system to achieve an accurate distribution of the thermal field.It is found that the use of a low radial temperature gradient leads to a flattening of the crystal interface and therefore to an extended facet with better crystallization.The hardness of the SiC is very close to that of diamond,making it extremely difficult to process large-diameter SiC crystals by cutting,lapping,polishing,etc.Low-warp and low-surface-roughness SiC wafers sliced by a diamond wire saw were obtained.The scratches and damage layer caused by lapping on the SiC wafer surface were reduced by chemo-mechanical polishing (CMP).After CMP,an extremely smooth and low damage layer surface with roughness Ra＜1nm was obtained.