1. Introduction

The increasing demand for commercial high-powered location-based services (LBSs) has led to higher requirements in terms of accuracy, coverage, and reliability that existing GPS-only designs are not be able to meet. The positioning solutions will be driven from sole GPS systems to multi-constellation/multi-frequency global navigation satellite systems (GNSSs) because the interoperability and compatibility among GNSSs such as GPS, GLONASS, Galileo, Compass (also known as Beidou-2) can significantly reduce the shaded range of the satellite signals and increase the number of the visible satellites in extreme environments to improve the positioning solution of the LBS^[1]. In order to support this interoperability and compatibility, two or more RF chips are always utilized to receive the GNSS signals simultaneously; however, this results in an increase of cost. Therefore, an evolution in fully integrated GNSS RF receiver design which can process the desired GNSS signals simultaneously is envisaged to enhance integrity and lower costs.

Traditionally, dual-band approaches for integrated GNSS RF receivers have been extensively employed, and those published in the past are mostly centralized on the use of GPS/Galileo systems^[2-6]. Recently, several successful implementations of fully integrated GNSS RF receivers including the Compass system in a CMOS process have been reported in Refs. ^[7-9] to improve the positioning solutions. All of them employ single-conversion low-IF architecture with the capability of processing different dual-bands of the GNSS signals simultaneously.

For the Compass region system, which will be expanded officially into a fully operational GNSS by 2020^[10] and has provided a positioning service to the Asia-Pacific region since Dec. 2012, it is foreseen that the demands of the GNSS receivers that depend on the Compass system will be dramatically increased. This paper presents a fully integrated dual-band RF receiver to support both the GPS-L1 and Compass-B1 bands. The dual-band receiver adopts single-conversion low-IF architecture, and incorporates two independent IF channels to receive the dual-band signals respectively. In order to save chip area and power consumption, and avoid LO crosstalk, the RF front-end and frequency synthesizer are shared for dual-band operation by implementing a flexible frequency plan. The receiver has been implemented in a 55 nm CMOS with excellent performances shown in the measurement results as compared with other state-of-the-art designs.

2. System design considerations

2.1 Channel gain and dynamic range

The thermal noise dominates the input power level of the receiver. For the GPS-L1 band, the noise level is about -110dBm, and for the Compass-B1 band it is about -107 dBm. For a 2-bit quantization ADC, the maximum output power level of the receiver is limited by the threshold voltage of the ADC and the ratio of the threshold to the root-mean-square (RMS)-noise level. Therefore, for a designed 2-bit ADC threshold of about 0.14 V and the ratio of 1 for the optimized ADC performance ($-4$ dBm noise level in a 50 Ω system), a nominal 106dB channel gain is needed for the GPS-L1 channel, and 103 dB for the Compass-B1 channel.

Generally, the total dynamic range of the receiver is determined by the gain variation introduced by external components (DR$_{1}$, active or passive antenna), environmental temperature (DR$_{2})$, and process and supply variation (DR$_{3})$. In this design, the DR$_{1}$ is set to less than 30 dB for passive/active antenna switching. The temperature-induced variation DR$_{2}$, which can be calculated from Ref. [11] if considering a temperature range from $-40$ to 100 ℃, is about 2 dB. Assuming that the worse gain variation DR$_{3}$ of the receiver is about $\pm$6 dB, thus, the required gain dynamic range of about 45 dB is sufficient for the dual-band receiver.

In this design, the maximum channel gain of the receiver is set to 122 dB. Considering the trade-off between the NF and linearity, the maximum gain of the RF front-end is set to 60 dB and the residue (62 dB) is distributed to the analog IF channel.

The full dynamic range is achieved by the combination of the adjustable gain from the RF front-end and analog IF channel. To achieve better receiver performance in the presence of interferences, an 82 dB gain dynamic range was implemented in the receiver. If a strong jamming signal exists in the signal band, then the lower bound of gain should be lowered to handle the large interfering signal. Thus, a 62 dB gain control range is provided by the analog IF channel, which is tunable from 0 to 62 dB with a 2 dB gain step. The gain control of the analog IF channel is realized using a digital AGC loop to achieve a constant signal magnitude at the ADC input for optimized ADC performance. The RF front-end provides a step gain of 20 dB, controlled by the baseband chip through the serial peripheral interface (SPI), to compensate the gain variation from the passive/active antenna switching. It will improve the anti-jamming capability of the receiver by increasing the downward range of gain variation of the AGC.

2.2 Receiver noise figure

For DSSS signals, the signal bandwidth varies with the position in the chip-set including radio and digital baseband, the precorrelation SNR is negative whereas postcorrelation SNR is positive. In order to ignore the effect of the bandwidth, it is convenient to normalize the SNR to a 1-Hz bandwidth, which refers to carrier-to-noise density ratio ($C/N_{0})$. Once the minimum required $C/N_{0}$ is given by a digital correlator in the baseband chip to maintain the wanted acquisition or tracking performance, the RF receiver sensitivity is uniquely determined by Eq. (2) without any confusion caused by the bandwidth ambiguity.

$\begin{array}{l} {\rm{Sensitivity}}[{\rm{dBm}}] = {\left( {\frac{C}{{{N_0}}}} \right)_{{\rm{rmmin}}}}\left[{{\rm{dB}} \cdot {\rm{Hz}}} \right] + {N_0}\left[{\frac{{{\rm{dBm}}}}{{{\rm{Hz}}}}} \right]\\ + {\rm{NC}}\left[{{\rm{dB}}} \right], \end{array}$

(1)

where $N_{0}$ is the thermal noise power density at the antenna port which equals to -174 dBm/Hz at typical room temperature and NC is the noise contribution of the receiver which is mainly derived from the insertion loss (IL) of the passive antenna or the thermal noise of the active antenna (NF of the active antenna), thermal noise of the receiver (NF of the receiver) and ADC conversion gain (Fig. 1). For a 2-bit quantization ADC, the conversion gain is about $-0.6$ dB when the thermal noise dominates the input power level and the threshold voltage of the ADC is equal to the RMS-noise level^[12].

As shown in Fig. 1, if a digital correlator requires the minimum $C/N_{0}$ of 25 dB$\cdot$Hz, the required NF of the receiver is 2.4dB for the sensitivity of -144 dBm with a passive antenna (IL $=$ 2 dB). The sensitivity will be improved and the required NF of the receiver could be relaxed (e.g., -146.3 dBm sensitivity and 6.5 dB NF) with an active antenna (Gain $=$ 20 dB, NF $=$ 2 dB).

2.3 Operating modes and frequency plan

The dual-band receiver supports three operating modes including simultaneous dual-band mode (GPS-L1 and Compass-B1) and single-band mode (GPS-L1 or Compass-B1). As shown in Fig. 2, in dual-band mode, GPS-L1 and Compass-B1 frequencies are translated into the IF frequencies of 10.23MHz and $-4.092$ MHz, respectively, with a LO located at 1565.19MHz. This choice of IF frequencies means that only one frequency synthesizer is required to save the power consumption and chip area, as well as avoiding LO crosstalk and reciprocal image interference between GPS-L1 and Compass-B1 signals. Hence, the primary requirement on image rejection is to reject the thermal noise in the image-band, and a relatively low-rejection of about 16 dB can preserve the in-band SNR^[11]. In single-band mode, the other channel is completely powered off to minimize power consumption. The GPS-L1 and Compass-B1 signals are translated into the IF frequency of 4.092 MHz and -4.092 MHz with the different LO frequencies centered at 1571.328 MHz and 1565.19 MHz respectively. The operating modes and frequency plan of the dual-band receiver are listed in Table 1.

The frequency synthesizer provides an output frequency range from 1.4-1.7 GHz to cover the required LO frequencies. To obtain less than 0.1 dB SNR loss, the averaged phase noise should be lower than -80 dBc/Hz^[11]. The on-chip reference of 16.368 MHz is adopted to avoid its high-order harmonics falling into the signal band. The ADC sampling clock and other calibration clock frequencies are 16.368 MHz derived from the divided LO signal or directly from the on-chip reference when the on-chip reference of 16.368 MHz is adopted to save chip power consumption.

3. Receiver architecture

A detailed block diagram of the dual-band receiver is shown in Fig. 3. The low-IF architecture is employed to improve the integration and avoid the issues associated with low-frequency noise, DC offset, and LO-leakage. Two independent IF channels are incorporated to support simultaneous dual-band reception. The other channel can be closed to reduce power consumption while only single-band operation is required to provide the LBS. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for dual-band operation to save power consumption and chip area, as well as avoid any LO crosstalk. The entire receiver uses differential signal processing to improve immunity to supply and substrate disturbances.

The LNA is placed at the interface to the antenna, and therefore dominates the noise behavior of the whole receiver. The following RFA further suppresses the noise introduced by the posterior~stages while a passive antenna is used. For active antenna, it will provide step gain attenuation of 20 dB to improve the anti-jamming capability of the receiver. After down-conversion by the quadrature mixer, the IF signal firstly gets I/Q mismatch calibration and then receives spectrum shaping by the reconfigurable complex BPF which provides channel selection, image rejection, and anti-aliasing. The PGA with digital AGC loop ensures a constant signal magnitude at the ADC input regardless of the received signal strength. Finally, the ADC quantizes the signal in 2-bit (SGN: sign, MAG: magnitude) with the 16.368 MHz sampling clock. The output of the ADC is applied to a digital signal processing unit, which performs the correlation and detection to determine the location. The quadrature LO signals for down-conversion are generated by the frequency synthesizer with the fractional-N phase-locked loop (PLL) architecture. The output of each channel can be taken before and after the ADC for testing and application flexibility.

A flexible scheme for power supply is utilized in the dual-band receiver to support different external supplies. As shown in Fig. 4, an external 3.3 V or 1.5 V supply can be adopted through the integrated power supply module including a DC-DC converter and an LDO to provide an internal 1.2 V supply for the dual-band receiver. For an external 3.3 V supply, a DC-DC converter is used to support energy-lossless voltage transfer from 3.3 to 1.5 V, its interference to the RF part is partly suppressed by the LDO achieving voltage transfer from 1.5 to 1.2 V. Good noise performance and a low bill-of-materials (BOM) can be acquired by switching the DC--DC converter to LDO with sacrificing power energy.

4. Circuits implementation

4.1 RF front-end

The RF front-end shared for the dual-band operation consists of an LNA, an RFA and a quadrature down-conversion mixer. As shown in Fig. 5, inductive degeneration cascode LNA topology is used to achieve simultaneous noise and input matching; the insertion of the coupled capacitor $C_{\rm c}$ adds a degree of freedom to achieve simultaneous noise and input matching at very low power dissipation without affecting the minimum NF^[13]. An L-type matching network is utilized to compensate the decrease of the input impedance due to the parasitical capacitance $C_{\rm p}$ introduced by the ESD circuit, bonding pad, and Miller effect of the $C_{\rm gd}$ of the M1 for the noise and input matching. The LC tank ($R_{\rm L}$ is the parasitic resistance of the inductor $L_{\rm L})$ structure is used to be the output load of the LNA, which will increase the DC voltage headroom for providing the same gain and effectively filter the large interferer signals for higher out-of-band linearity performance comparing with the traditional resistor load. The simulation NF and gain of this LNA is 1.2 dB and 25 dB at 1.57 GHz respectively, for setting $C_{\rm p}$ $=$ 400 fF, adequate to suppress the noise contribution from the subsequent stages. The over-drive voltage of the M1a, b is set to 0.15 V to lower the power consumption of the LNA with the adequate linearity performance, the simulated IIP3 is larger than -6 dBm at 1.57 GHz. The whole current consumption of the LNA is about 2.5 mA.

The cross-coupled differential pair M3a, M3b is added for an automatic LC calibration to obtain constant center frequency against PVT variations. If a clock signal $f_{\rm LO}$ (in the middle between the GPS-L1 signal and the Compass-B1 signal) from the PLL is detected, the LNA enters the oscillation mode to generate an $f_{\rm cal}$ signal whose frequency is determined by the LC-tuned resonator. Then, the proposed LC calibrator, shown in Fig. 6, finds the desired code for a capacitor bank by comparing the LO signal $f_{\rm LO}$ from the PLL with the $f_{\rm cal}$ signal through a binary search method. The calibration process is described as follows: the $f_{\rm cal}$ signal is counted to $N_{\rm cal}$ through the counter during a period $T_{\rm GATE}$ which is the high level duration of the clock signal $f_{\rm LO}$ divided by 4$m$ ($m$ $=$ 64 in this design). The target number $N_{\rm LO}$ is obtained from the register which is written to 2m in advance. Afterwards, the frequency error $\delta$ between the target frequency and the calibration frequency is generated by a comparator. The binary search scheme shifts the frequency code (FC) to generate the corresponding FCC through the encoder according to the sign of the error. A minimum error register is used to store the latest minimum frequency error and its corresponding frequency control code (FCC). Lastly, the FCC corresponding to minimum frequency error will be chosen to calibrate the LC resonation frequency.

The following RFA using common-source architecture is inserted between the LNA and the mixer to improve the noise performance and provide gain control for a large dynamic range. The digital logic signal S is used to provide the gain variation of the RFA for compensating the gain variation due to the antenna switching to decrease the linearity requirement for the subsequent stages and improve the anti-jamming capacity of the receiver. The input transconductance of the RFA is set to be 15 mS for good noise performance and low power consumption, and the load resistor is set to be 670 Ω. The simulated NF of the RFA is approximately 3.2 dB while the current consumption is about 1.5 mA.

A pair of Gilbert-type double-balanced mixers shown in Fig. 7 is modulated using 4-path quadrature LO signals to realize I/Q down-conversion, where the RF signals are shifted to the IF bands and divided into in-phase and quadrature paths. The current bleeding technique is used for both the load resistors and switching transistors, in order to enlarge the voltage headroom and reduce flicker noise from the MOSFETs. Also, the current reuse technique is used to increase the power gain without consuming additional DC current. The pseudodifferential solution is better suited for high IIP3, due to the grounded common source. It will save about 0.1-0.2 V voltage headroom for the same IIP3 comparing with the fully differential structure, indicating the topology is applicable to low supply voltage applications. Since larger transconductance helps to suppress noise and larger over-drive voltage is beneficial for linearity, and considering the gain of the fore-circuits including LNA and RFA is about 45 dB, so the input transconductance and over-drive voltage are set to be 3 mS and 0.2 V respectively with 0.3 mA DC current consumption in each path. The simulation result shows that the mixer achieves 15 dB conversion gain to further suppress the noise contribution of the substantial stages and single sideband (SSB) NF of about 11 dB.

4.2 Image-rejection complex filter

The image-rejection complex filter integrated in this receiver is a fourth-order BPF, with its center frequency and bandwidth reconfigurable for different operational bands and modes. The complex BPF selects the dual-band signals with rejecting the image and out-of-band spurious signals and noise, either down-converted by RF front-end, or directly coupled by the substrate, as well as providing an anti-aliasing function before the IF ADC. As shown in Fig. 8, the complex BPF is implemented by means of two real low-pass filters (LPFs) quadrature coupled through cross-coupled resistors ($R_{\rm c})$ to achieve the central frequency transfer from baseband to IF frequency. An active-RC Butterworth-type solution with a leapfrog structure has been selected to improve linearity and ruggedness versus interferers. The on/off switches (SW) control the selection of the positive or negative side band-pass function. In order to cover the three operating modes, the complex BPF provides central frequencies of 4.092 MHz and 10.23 MHz and bandwidth of 2.046 MHz and 4.092 MHz, respectively. An on-chip RC auto-calibration mechanism activated at power up accurately sets up the central frequency and bandwidth by adjusting the filter RC time constant against process and temperature variations. The complex BPF consumes about 3 mA current from a 1.2 V supply, it has more than 35 dB image rejection, input referred noise voltage of about 30 nV/Hz$^{1/2}$ (about 30dB NF referred to 50 Ω), and input 1 dB compression point of about 5.4 dBm.

4.3 PGA and auto-adaptive digital AGC loop

A multistage PGA with a digital AGC loop is implemented in this receiver. The PGA contains four stages of variable gain amplifier (VGA) based on a fully differential op-amp with resistor network feedback, with a high-pass RC filter inserted at the PGA's input terminal and output terminal to eliminate the DC offset^[14]. In order to realize a large dynamic range with fine adjustment steps, the gain-distribution is arranged carefully, where different gain ranges and steps are distributed among the stages, as listed in Table 2.

The gain of the PGA is controlled automatically by monitoring the output of the ADC through the digital AGC loop to compensate for process and temperature variation of the receiver gain and also to accommodate in-band jammers without saturating the receiver, as shown in Fig. 9. To minimize the loss of the SNR and design complexity, a 2-bit flash ADC (1-bit SGN and 1-bit MAG), which is similar to that used in Ref. [6], is utilized in this paper. The AGC loop sets the gain of the PGA so the duty cycle of the MAG bit is about 33% when the thermal noise with Gaussian distribution dominates the receiver's input power level, which is known to provide negligible SNR loss of about 0.6 dB^[12]. The duty cycle of the MAG bit can represent the Gaussian noise power. In this work, a simple counter is used as a power detector. The counter counts the number of ones in every n cycle to calculate the duty cycle error of the MAG bit by comparing it with the programmable digital threshold $N_{\rm TH}$ (it initially equals $n$/3, and can be adjusted by the baseband to obtain the optimum conversion gain of the ADC when the jamming is much stronger than the thermal noise^[15]. Then the look-up table (LUT) integrated to improve the calibration time generates the corresponding gain step (2 dB, 4 dB, 6 dB, 8 dB and 16 dB) according to the value of the error. The integrator is realized using a multi-bit accumulator to provide the gain control codes through the decoder. A dead zone block, which tolerates about $\pm$1 dBm power error, is also included to avoid instability of the AGC loop.

4.4 Frequency synthesizer

A fractional-$N$ PLL synthesizer, using a third-order ΣΔ modulator with a 24-bit accumulator, is employed to generate a wide frequency output from 1.4 to 1.7 GHz with frequency step of less than 1 Hz by using one VCO with a complementary cross-coupled architecture. In order to provide 4-phase LO signals for the quadrature mixer, the VCO works at twice the LO frequency and then divided by 2. As far as phase noise is concerned, the entire tuning range of the VCO is divided into 16 sub-bands by a 4-bit capacitor bank to decrease the voltage-to-frequency gain ($K_{\rm VCO})$. The loop filter is of third order to suppress the out-of-band phase noise generated from the ΣΔ modulator. The loop filter is implemented with the resistance and capacitance arrays to support the multiple reference clocks. The reference frequency of the synthesizer is 16.368 MHz, and the cascade 2/3 TSPC divider is adopted in the programmable divider to cover the desired divide ratio. During the frequency range from 1.4 to 1.7 GHz, the frequency band step is 40 MHz uniformly and the average voltage-frequency gain $K_{\rm VCO}$ of the VCO is 85 MHz/V. The source and sink current $I_{\rm CP}$ of the charge pump is 80 $\mu$A. The closed-loop bandwidth of the PLL is designed to 60 kHz, and the phase margin is about 60$^\circ$.

5. Experimental results

The dual-band receiver for GPS-L1 and Compass-B1 is implemented in a 55 nm CMOS process and housed in a standard 5 $\times$ 5 mm$^{2}$ 32-pin QFN package. The die photo of the chip is shown in Fig. 10, with an active chip area of 1.5 $\times$ 1.4 mm$^{2}$ including ESD and I/O pads. The entire signal path is differentially configured and symmetrically routed for better common noise/interference immunity. Key building blocks are placed in separate deep n-wells for further noise isolation.

The measured voltage-"standing-wave"-ratio (VSWR), as shown in Fig. 11, is about 1.4 ($S_{11}$ $=$ -15.6 dB) both at 1575.42MHz for GPS-L1 and 1561.098 MHz for Compass-B1 with the input impedance well-matched to 50 Ω at 1.57 GHz. The measured output frequency response of the dual-band receiver at three different modes (i.e., different central frequency and bandwidth for simultaneous or single receiving) with the input level of $-85$ dBm at the gain setting of 60 dB is shown in Fig. 12. The different central frequencies (4.092 MHz and 10.23 MHz) and bandwidths (2.046 MHz and 4.092 MHz) can be provided for different working modes.

The synthesizer locking range has been measured under temperature ($-40$$^\circ$, 25$^\circ$, 100$^\circ)$ variation and all exceed the required 1.4-1.7 GHz range, and the output frequency deviations at 1565.19 MHz and 1571.328 MHz for different temperature are both less than 1 kHz. Figure 13 presents the IF phase noise at 100 Hz, 1 kHz, 10 kHz and 100 kHz offset measured at the receiver output ports (GPS-L1 channel and Compass-B1 channel, respectively) at room temperature. The average in-band (0.1-100 kHz) phase noise is less than $-80$ dBc/Hz, and the out-of-band phase noise at 1 MHz offset is about $-112$ dBc/Hz. It is enough to meet the phase noise requirement of the dual-band receiver.

The measured IMRs are 35.38 dB and 36.65 dB for GPS-L1 channel and Compass-B1 channel respectively, as shown in Fig. 14, the measured image frequency point is located at 1554.96 MHz ($-20.46$ MHz offset corresponding to GPS-L1 frequency point) for GPS-L1 signal, and 1569.282MHz (8.184MHz offset corresponding to Compass-B1 frequency point) for Compass-B1 signal with the input power of $-80$dBm at the gain setting of 80 dB.

The output IF spectrum with an input power of $-94$ dBm and noise spectrum without an input signal for the dual-band channels at the gain setting of 90 dB (RFA: 20 dB, passive antenna application) are shown in Fig. 15, the measured output signal power and noise power spectral density (PSD) are $-3.983$ dBm and $-80.48$ dBm/Hz for GPS-L1 channel, and $-4.758$ dBm and $-81.52$ dBm/Hz for Compass-B1 channel. The NF of the receiver for the dual-band channels can be obtained by the following equation:

$\begin{array}{l} {\rm{NF}} = {\rm{SN}}{{\rm{R}}_{{\rm{in}}}} -{\rm{SN}}{{\rm{R}}_{{\rm{out}}}} -{\rm{IL}}\\ = 174{\mkern 1mu} {\rm{dBm/Hz}} + {P_{{\rm{n}}\_{\rm{PSD}}}} -G - {\rm{IL}}, \end{array}$

(2)

where the $P_{\rm n\_PSD}$ is the noise PSD, $G$ is the gain of the receiver, and IL of about 1.4 dB is the insertion loss of the SMA cable and the LC balun. So we can acquire the NF of the dual-band channels as follows:

$\begin{array}{l} {\rm{N}}{{\rm{F}}_{{\rm{GPS - L1}}}} = {\rm{174}}{\mkern 1mu} {\rm{dBm/Hz - 80}}.{\rm{48}}{\mkern 1mu} {\rm{dBm/Hz}}\\ - [{\rm{-3}}.{\rm{983}}{\mkern 1mu} {\rm{dBm-}}({\rm{-94}}{\mkern 1mu} {\rm{dBm}})]{\rm{ - 1}}.{\rm{4}}{\mkern 1mu} {\rm{dB}}\\ = 2.103{\mkern 1mu} {\rm{dB}}, \end{array}$

(3)

$\begin{array}{l} {\rm{N}}{{\rm{F}}_{{\rm{Compass - B1}}}} = {\rm{174}}{\mkern 1mu} {\rm{dBm/Hz - 81}}.{\rm{52}}{\mkern 1mu} {\rm{dBm/Hz}}\\ - [{\rm{-4}}.{\rm{758}}{\mkern 1mu} {\rm{dBm-}}({\rm{-94}}{\mkern 1mu} {\rm{dBm}})]{\rm{ - 1}}.{\rm{4}}{\mkern 1mu} {\rm{dB}}\\ = 1.838{\mkern 1mu} {\rm{dB}}. \end{array}$

(4)

For the active antenna application, the gain of the RFA is set to 0 dB, the measured NF of the GPS-L1 channel is about 3.3 dB and the Compass-B1 channel is about 2.7 dB. The degradation of the NF can be neglected because of the gain of the active antenna.

As shown in Fig. 16, the input-referred 1-dB compression point is about -56 dBm with the minimum gain setting of 60 dB (RF front-end: 60 dB, analog IF channel: 0 dB) when utilizing the passive antenna, but it will be raised to about -36.5 dBm with the minimum gain setting of 40 dB (RF front-end: 40 dB, analog IF channel: 0 dB) while the active antenna is used.

The measured performance of the dual-band receiver is summarized in Table 3, and the performance comparison is also shown. As can be seen, most performance of the proposed dual-band receiver is better than or as good as other state-of-the-art devices and it occupies the smallest active silicon area. Moreover, benefitting from design optimizations, the noise figure of the receiver can be maintained within the lowest level compared to the previous studies while the passive antenna is applied.

6. Conclusions

This paper describes a dual-band GNSS receiver with low-IF architecture for high-powered LBSs in a 55 nm CMOS process. The receiver embodies two independent IF channels to support GPS-L1 and Compass-B1 signals, and can provide three operational modes (GPS-L1 and Compass-B1, GPS-L1, Compass-B1) with either passive or active antenna. The RF front-end and frequency synthesizer are shared to save power consumption and chip area, as well as avoiding any LO crosstalk. A step gain is provided by the RF front-end to compensate the gain variation due to the antenna switching, which will effectively improve the anti-jamming capability of the receiver. A digital AGC loop is integrated to improve the receiver's robustness by optimizing the conversion gain of the ADC. While drawing about 20 mA per channel from a 1.2V supply, this RF receiver achieves a minimum NF of about 1.8dB, IMR of more than 35 dB, maximum voltage gain of about 110 dB, gain dynamic range of more than 68 dB, and $P_{\rm 1dB}$ of about -36.5 dBm with an active die area of 1.5 $\times$ 1.4mm$^{2}$ for the whole chip.