Fig. 1.
Single-ended architecture and its timing diagram of SAR ADC. (a) Conventional. (b) Proposed with comparator-sharing technique
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| Citation: |
Chenghao Bian, Jun Yan, Yin Shi, Ling Sun. A 130 nm CMOS low-power SAR ADC for wide-band communication systems[J]. Journal of Semiconductors, 2014, 35(2): 025003. doi: 10.1088/1674-4926/35/2/025003
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C H Bian, J Yan, Y Shi, L Sun. A 130 nm CMOS low-power SAR ADC for wide-band communication systems[J]. J. Semicond., 2014, 35(2): 025003. doi: 10.1088/1674-4926/35/2/025003.
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A 130 nm CMOS low-power SAR ADC for wide-band communication systems
DOI: 10.1088/1674-4926/35/2/025003
More Information
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Abstract
This paper presents a low power 9-bit 80 MS/s SAR ADC that uses the comparator-sharing technique in a 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The 'set-and-down' switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.-
Keywords:
- ADC,
- SAR,
- capacitor-sharing,
- error compensation,
- capacitor array,
- dynamic logic
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References
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