J. Semicond. > 2014, Volume 35 > Issue 2 > 025005
|

SEMICONDUCTOR INTEGRATED CIRCUITS

An effective timing characterization method for an accuracy-proved VLSI standard cell library

Jianhua Jiang, Man Liang, Lei Wang and Yumei Zhou

+ Author Affiliations

 Corresponding author: Jiang Jianhua, Email:jiangjianhua@ime.ac.cn

DOI: 10.1088/1674-4926/35/2/025005

PDF

Abstract: This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

Key words: characteristic parameters, error calculation, look-up table, Lib file



[1]
Zhang K, Wang D H, Li Y G. Library building for sub-micron CMOS process. Fifth International IEEE Conference on ASIC, 2003:1369
[2]
Library CompilerTM Modeling Timing, Signal Integrity, and Power in Technology Libraries User Guide
[3]
Scheffer L. EDA for IC implementation, circuit design, and process technology. Addision-Wesley, Reading
[4]
Gao Mingzhi, Ye Zuochang, Wang Yan, et al, On modeling the digital gate delay under process variation. Journal of Semiconductors, 2011, 32(7):075010 doi: 10.1088/1674-4926/32/7/075010
[5]
Ackalloor B, Gaitonde D. An overview of library characterization in semi-custom design. IEEE Custom Integrated Circuits Conference, 1998
[6]
Rachit I K, Bhat M S. AutoLibGen:an open source tool for standard cell library characterization at 65nm technology. International Conference on Electronic Design Penang, Malaysia, 2008 http://ieeexplore.ieee.org/document/4786726/authors
[7]
Miryala S, Kaur B, Anand B, et al. Efficient nanoscale VLSI standard cell library characterization using a novel delay model. 12th Int'l Symposium on Quality Electronic Design, 2011 http://ieeexplore.ieee.org/document/5770767/keywords
[8]
LibertyTM NCX User Guide Version B, December 2008
Fig. 1.  An example cell delay arc

DownLoad: Full-Size Img PowerPoint
Fig. 2.  NLDM calculation schematic

DownLoad: Full-Size Img PowerPoint
Fig. 3.  Coordinate for linear interpolation

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Variation of characteristic values with output load capacitance ($C_{\rm l})$. (a) Cell fall. (b) Cell rise. (c) Rise transition. (d) Fall transition

DownLoad: Full-Size Img PowerPoint
Fig. 5.  Variation of characteristic values with input transition time ($C_{\rm l})$. (a) Cell fall. (b) Cell rise. (c) Rise transition. (d) Fall transition

DownLoad: Full-Size Img PowerPoint
Fig. 6.  Logarithmic distribution histogram

DownLoad: Full-Size Img PowerPoint
Fig. 7.  Uniform distribution histogram

DownLoad: Full-Size Img PowerPoint
Fig. 8.  Normal distribution histogram

DownLoad: Full-Size Img PowerPoint
Fig. 9.  Schematic of C17

DownLoad: Full-Size Img PowerPoint
Fig. 10.  Layout of C17

DownLoad: Full-Size Img PowerPoint

Table 1.   Coefficient values for fall cell delay

Table 2.   Correspondence value of MCy and yield

Table 3.   Correspondence value of MCy and yield
[1]
Zhang K, Wang D H, Li Y G. Library building for sub-micron CMOS process. Fifth International IEEE Conference on ASIC, 2003:1369
[2]
Library CompilerTM Modeling Timing, Signal Integrity, and Power in Technology Libraries User Guide
[3]
Scheffer L. EDA for IC implementation, circuit design, and process technology. Addision-Wesley, Reading
[4]
Gao Mingzhi, Ye Zuochang, Wang Yan, et al, On modeling the digital gate delay under process variation. Journal of Semiconductors, 2011, 32(7):075010 doi: 10.1088/1674-4926/32/7/075010
[5]
Ackalloor B, Gaitonde D. An overview of library characterization in semi-custom design. IEEE Custom Integrated Circuits Conference, 1998
[6]
Rachit I K, Bhat M S. AutoLibGen:an open source tool for standard cell library characterization at 65nm technology. International Conference on Electronic Design Penang, Malaysia, 2008 http://ieeexplore.ieee.org/document/4786726/authors
[7]
Miryala S, Kaur B, Anand B, et al. Efficient nanoscale VLSI standard cell library characterization using a novel delay model. 12th Int'l Symposium on Quality Electronic Design, 2011 http://ieeexplore.ieee.org/document/5770767/keywords
[8]
LibertyTM NCX User Guide Version B, December 2008

    • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 5551 Times PDF downloads: 75 Times Cited by: 0 Times

    History

    Received: 05 July 2013 Revised: 28 August 2013 Online: Published: 01 February 2014

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2014  >  35(2): 025005
      Jianhua Jiang, Man Liang, Lei Wang, Yumei Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. Journal of Semiconductors, 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005 ****J H Jiang, M Liang, L Wang, Y M Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. J. Semicond., 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005.
      Citation:
      Jianhua Jiang, Man Liang, Lei Wang, Yumei Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. Journal of Semiconductors, 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005 ****
      J H Jiang, M Liang, L Wang, Y M Zhou. An effective timing characterization method for an accuracy-proved VLSI standard cell library[J]. J. Semicond., 2014, 35(2): 025005. doi: 10.1088/1674-4926/35/2/025005.
      shu

      An effective timing characterization method for an accuracy-proved VLSI standard cell library

      DOI: 10.1088/1674-4926/35/2/025005

      • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      Funds:

      Project supported by the National Science and Technology Major Project (No. 10ZX02305-013-002/10ZX02305-013-004)

      the National Science and Technology Major Project 10ZX02305-013-002

      the National Science and Technology Major Project 10ZX02305-013-004

      More Information
      • Corresponding author: Jiang Jianhua, Email:jiangjianhua@ime.ac.cn
      • Received Date: 2013-07-05
      • Revised Date: 2013-08-28
      • Published Date: 2014-02-01

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return