A novel symmetrical split-gate structure for 2-bit per cell flash memory

Liang Fang; Weiran Kong; Jing Gu; Bo Zhang; Shichang Zou

doi:10.1088/1674-4926/35/7/074008

J. Semicond. > 2014, Volume 35 > Issue 7 > 074008

SEMICONDUCTOR DEVICES

A novel symmetrical split-gate structure for 2-bit per cell flash memory

Liang Fang^{1, 2, 3,}, Weiran Kong², Jing Gu², Bo Zhang² and Shichang Zou^{1, 3}

+ Author Affiliations

Corresponding author: Fang Liang, Email:fangliang@mail.sim.ac.cn

DOI: 10.1088/1674-4926/35/7/074008

Abstract: A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection (SSI) and a poly-to-poly tunneling mechanism respectively.

Key words: split-gate flash, 2-bit per cell, self-aligned process

References

[1]	Houdt J V, Haspeslagh L, Wellekens D, et al. HIMOS-a high efficiency flash E2PROM cell for embedded memory applications. IEEE Trans Electron Devices, 1993, 40: 2255 doi: 10.1109/16.249473
[2]	Cho C Y S, Chen M J, Chen C F, et al. A novel self-aligned highly reliable sidewall split-gate flash memory. IEEE Trans Electron Devices, 2006, 53: 465 doi: 10.1109/TED.2005.863764
[3]	Shih H S, Fang S W, Kang A C, et al. High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory. Appl Phys Lett, 2008, 93: 213503 doi: 10.1063/1.3023057
[4]	Chu W T, Lin H H, Hsieh C T, et al. Shrinkable triple self-aligned field-enhanced split-gate flash memory. IEEE Trans Electron Devices, 2004, 51: 1667 doi: 10.1109/TED.2004.835995
[5]	Wu M Y, Lin H H, Hu S F, et al. Highly scalable ballistic injection AND-type (BiAND) flash memory. IEEE Trans Electron Devices, 2006, 53: 109 doi: 10.1109/TED.2005.860636
[6]	Eitan B, Pavan P, Bloom I, et al. NROM: a novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Device Lett, 2000, 22: 543 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=877205&contentType=Journals+%26+Magazines
[7]	Houdt J V, Wellekens D, Groeseneken G, et al. Investigation of the soft-write mechanism in source-side injection flash EEPROM devices. IEEE Trans Electron Devices, 1995, 16: 181 doi: 10.1109/55.382233
[8]	Breuil L, Haspeslagh L, Blomme, et al. A new scalable self-aligned dual-bit split-gate charge-trapping memory device. IEEE Trans Electron Devices, 2005, 52: 2250 doi: 10.1109/TED.2005.856803
[9]	Lue H T, Hsu T H, Wu M T, et al. Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model. IEEE Trans Electron Devices, 2006, 53: 119 doi: 10.1109/TED.2005.860644
[10]	Yuri T, Xian L, Alexander K. Floating-gate corner-enhanced poly-to-poly tunneling in split-gate flash memory cells. IEEE Trans Electron Devices, 2012, 59: 5 doi: 10.1109/TED.2011.2171346

Fig. 1. Schematic diagram of this flash cell.

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Fig. 2. Illustration of the process flow.

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Fig. 3. The measured I-V characteristics, second-bit-effect and read operations of bit1 for this cell.

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Fig. 4. Gate (I_G) and drain (I_D) current measured in a dummy cell (FG and CG are connected). Bias conditions are illustrated in the inset to simulate the program condition. For programming, V_SG = 1.3 V is chosen in consideration of the process variation cell-by-cell and low current program ability (about 1 μA) is obtained.

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Fig. 5. Simulated lateral and vertical electric field along the channel surface under the programming conditions, which are depicted in the inset of Fig. 4. High lateral and vertical electric field are simultaneously obtained.

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Fig. 6. Measured program and erase characteristics for this flash memory cell. Bias conditions refer to Table 1. The threshold voltage is measured in a reverse-read scheme.

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Table 1. Cell operation conditions (Unit: V).

[1]	Houdt J V, Haspeslagh L, Wellekens D, et al. HIMOS-a high efficiency flash E2PROM cell for embedded memory applications. IEEE Trans Electron Devices, 1993, 40: 2255 doi: 10.1109/16.249473
[2]	Cho C Y S, Chen M J, Chen C F, et al. A novel self-aligned highly reliable sidewall split-gate flash memory. IEEE Trans Electron Devices, 2006, 53: 465 doi: 10.1109/TED.2005.863764
[3]	Shih H S, Fang S W, Kang A C, et al. High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory. Appl Phys Lett, 2008, 93: 213503 doi: 10.1063/1.3023057
[4]	Chu W T, Lin H H, Hsieh C T, et al. Shrinkable triple self-aligned field-enhanced split-gate flash memory. IEEE Trans Electron Devices, 2004, 51: 1667 doi: 10.1109/TED.2004.835995
[5]	Wu M Y, Lin H H, Hu S F, et al. Highly scalable ballistic injection AND-type (BiAND) flash memory. IEEE Trans Electron Devices, 2006, 53: 109 doi: 10.1109/TED.2005.860636
[6]	Eitan B, Pavan P, Bloom I, et al. NROM: a novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Device Lett, 2000, 22: 543 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=877205&contentType=Journals+%26+Magazines
[7]	Houdt J V, Wellekens D, Groeseneken G, et al. Investigation of the soft-write mechanism in source-side injection flash EEPROM devices. IEEE Trans Electron Devices, 1995, 16: 181 doi: 10.1109/55.382233
[8]	Breuil L, Haspeslagh L, Blomme, et al. A new scalable self-aligned dual-bit split-gate charge-trapping memory device. IEEE Trans Electron Devices, 2005, 52: 2250 doi: 10.1109/TED.2005.856803
[9]	Lue H T, Hsu T H, Wu M T, et al. Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model. IEEE Trans Electron Devices, 2006, 53: 119 doi: 10.1109/TED.2005.860644
[10]	Yuri T, Xian L, Alexander K. Floating-gate corner-enhanced poly-to-poly tunneling in split-gate flash memory cells. IEEE Trans Electron Devices, 2012, 59: 5 doi: 10.1109/TED.2011.2171346

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Received: 18 December 2013 Revised: 26 January 2014 Online: Published: 01 July 2014

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection (SSI) and a poly-to-poly tunneling mechanism respectively.

A novel symmetrical split-gate structure for 2-bit per cell flash memory

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