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J. Semicond. > 2015, Volume 36 > Issue 9 > 095002

SEMICONDUCTOR INTEGRATED CIRCUITS

On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu and Xuecheng Zou

+ Author Affiliations
DOI: 10.1088/1674-4926/36/9/095002

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Abstract: Three linear CMOS power amplifiers (PAs) with high output power (more than watt-level output power) for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer (PCT) and one 1.95 GHz PA using an on-chip series combining transformer (SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors (MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.

Key words: CMOSlinearitypower combinertransformerspower amplifier

With silicon CMOS devices scaled into the deep submicrometer regime,using Ge as the channel material to fabricate germanium-on-insulator (GeOI) MOSFETs has become a hot research topic,due to its high mobility and performances[1, 2, 3, 4, 5, 6],in which the carrier mobility in the channel is one of the most concerned topics. In 2008,Bedell et al. demonstrated that high hole mobility can be maintained with the gate lengths down to 65 nm in partially strained (0.5%) Ge p-channel MOSFETs fabricated on silicon-germanium-on-insulator (SGOI) substrates[7]. In 2010,Gu et al. used ultra-thin thermal GeO$_{2}$ as the passivation layer to prepare GeOI pMOSFETs with a high quality interface and obtained a peak hole mobility of 260 cm$^{2}$/(V$\cdot$s) at room temperature[8]. In 2013,Lee et al. investigated the depth profiling of GeOI crystallinity by using Raman spectroscopy and confirmed that the difference of Ge crystallinity in the front channel from that in the back one was an important mechanism of mobility degradation in ultra-thin body GeOI nMOSFETs[9]. In 2014,Hosoi et al. reported a very high peak hole mobility of 511 cm$^{2}$/(V$\cdot$s) in pseudo-GeOI pMOSFETs with back-gate controlled striped Ge channels fabricated by lateral liquid-phase epitaxy (LLPE),showing that LLPE is a promising technique to prepare next-generation GeOI MOS devices with high mobility[10].

Although many fruitful results have been achieved in the experimental investigation on carrier mobility of GeOI MOSFETs,the theoretical model on the mobility was less involved. In 2011,Daele[11] presented a simple empirical model on the hole mobility,but the micro-physical mechanisms could not be clearly revealed by his model. So,the aim of this work is to establish a physically based hole mobility model of GeOI pMOSFETs by comprehensively analyzing the scattering mechanisms,e.g. acoustic phonon scattering,ionized impurity scattering,surface roughness scattering,coulomb scattering,and so on. The correctness and validity of the model are confirmed by comparing with experimental data. Moreover,some useful results are obtained by using this model to discuss the effects of temperature,surface roughness,the interface charges,channel doping concentration and the thickness of Ge film on inversion channel mobility of GeOI pMOSFETs in detail.

The structure of GeOI pMOSFETs is shown in Figure1,where $T_{\rm GeOI}$ and $T_{\rm oxb}$ are the thicknesses of the n-type Ge film and buried oxide layer,respectively,$L$ is the channel length,and a high-$k$ material is used as the gate dielectric. Based on Fermi's Golden Rule[12],the scattering probability of carriers in semiconductors can be expressed as:

Pkk=1τkk=2π|Mkk|2δ(EkEk±w),

where $P_{ kk'}$ is the scattering probability of carriers from the k state to the $\boldsymbol {k'}$ state,$\tau_{ kk'}$ is the relaxation time,$M_{ kk'}$ is the scattering matrix element,the $\delta$ function is the condition for energy conservation,while $\hbar$ and $\omega$ are the Planck constant and the phonon frequency ($\hbar \omega$ is phonon energy),respectively. When the elastic scattering happens on the carriers,$\hbar \omega$ equals to zero. Fortunately,the ionized impurity scattering is elastic scattering and acoustic phonons scattering can be approximately treated as elastic scattering because the energy of electrons or holes is higher than that of the phonons so that when electrons or holes are scattered by phonons,their energy change can be ignored as compared with their average energy.

Figure  1.  The schematic diagram of a GeOI pMOSFET structure.

In the following paragraphs,the effects of different scattering mechanisms on the hole mobility in the inversion channel will be investigated in detail.

Assuming that hole carriers in the inversion layer are two-dimensional hole gas and occupy only the lowest subband,the mobility determined by acoustic phonon scattering can be described as follows[13, 14]:

Pac=1τac=mdD2ackbT3ρv2s|ζm(z)|2|ζn(z)|2dz,

and the corresponding hole mobility can be calculated as:

μac=eτacm,

where $\tau_{\rm ac}$ is the relaxation time of acoustic phonon scattering,$m_{\rm d}$ and $m^{\ast}$ are the density-of-state mass and conductivity mass,respectively; $e$ is the elemental charge,$D_{\rm ac}$ is the deformation potential for the acoustic phonon scattering,$\rho$ is the density of Germanium,$v_{\rm s}$ is the velocity of phonons in Ge with $v_{\rm s}^{2 }=v_{l}^{2 }+v_{\rm t}^{2 }$[15] ($v_{\rm l}$ and $v_{\rm t}$ are the longitudinal and transverse velocity of phonons,respectively),$\zeta_{\rm m}(z)$ and $\zeta_{\rm n}(z)$ are the envelope function of two dimensional carriers in $m$-th and $n$-th subband. According to the results given by Stern and Howard[16],the integral in Equation (2) can be rewritten as:

(|ζm(z)|2|ζn(z)|2dz)1=163(ε0εs212me2)1/3×(Ndepl+1132Ns)1/3,

where $N_{\rm s}$ and $N_{\rm depl}$ are the inversion-charge areal density and effective depletion-charge areal density,respectively,while $\varepsilon_{0}$ and $\varepsilon_{\rm s}$ are the vacuum permittivity and the relative permittivity of Ge,respectively. In fact,the hole mobility described by Equation (2) is related to the effective electric field ($E_{\rm eff})$ at the high-$k$/Ge interface[17]:

Eeff=eε0εs(Ndepl+ηNs)+εoxbεsVbToxb,

where $\varepsilon_{\rm oxb}$ is the relative permittivity of the buried oxide layer,$V_{\rm b}$ is the substrate bias and the $\eta$ factor is 1/3 for holes in bulk Si and Ge[18],however,it changes slightly with the inversion-charge areal density in GeOI MOSFETs,implying that the $\eta$ factor depends on device architecture,and its average value for GeOI MOSFETs is found to be around 0.40[11]. Besides,as can be seen from Eq. (5),$E_{\rm eff}$ is also a function of $N_{\rm s}$.

Brooks-Herring approximation can be used to describe the ionized impurity scattering when the doping concentration of the channel is below 10$^{18 }$ cm$^{-3}$. The screening coulomb potential in a nondegenerate case can be expressed as:

V(r)=e4πε0εsrexp(βsr),

β2s=ne2ε0εskbT,

where $\beta_{\rm s}$ is the inverse screening length and $n$ is the concentration of ionized impurity.

According to Reference [19],the Brooks-Herring formula can be written as:

PI=1τI=V4π2k11(1ξ)Pi(k,k)k2dkdξ,

Pi(k,k)=2πNe2V|V(q1)|2δ(EkEk),
V(q1)=V(r)exp(iq1r)dr,

in which $V$($q_{1})$ is the Fourier coefficient of $V$(r),$P_{\rm i}(\boldsymbol{k},\boldsymbol{k'})$ is the scattering probability of the holes per unit volume by the ionized impurity scattering center and $\tau_{\rm I}$ is the relevant scattering relaxation time. Substituting Equations (6),(7),(9) and (10) into Equation (8) and using the formula of $\mu _{\rm I} =\frac{e \tau _{\rm I}}{m^\ast }$,the mobility limited by ionized impurity scattering can be worked out:

μI=162π(ε0εs)2E3/20Nde3m1/2[ln(1+a)a1+a]1,

where $a=\frac{8m^\ast E_0}{\hbar ^2\beta _{\rm s}^2 }$,$N_{\rm d}$ is the doping concentration in the channel (assuming that all the impurities are ionized at room temperature,then $n =N_{\rm d})$,and $E_{0}$ is the thermal energy ($E_{0}$ $=$ 3/2$k_{\rm b}T$[15]). The Born approximation presupposes that $a$ $\gg$ 1,so that the quantity within the bracket in Equation (11) may be replaced by ln$a$[19]. Thus,Equation (11) can be rewritten as:

μI=162π(ε0εs)2E3/20Nde3m1/2lna.

Assuming that $\Delta $$(\boldsymbol r')$ is a thickness deviated from its average position,as shown in Figure2,the perturbation Hamiltonian can be calculated by[20]:

HSR=eV(z)eV[z+Δ(r)]=eΔ(r)tialV(z)tialz=eΔ(r)Eeff.

Figure  2.  Schematic model for the roughness of the high-$k$ dielectric/Ge interface,in which the dashed line represents the average position of the interface.

Assuming that the correlation function $C(\boldsymbol r)=\langle\Delta(\boldsymbol {r'}),\Delta (\boldsymbol{r'}+\textbf{r})\rangle$ described the roughness obeys the exponential distribution,the power spectral density can be found by Fourier transform of $C(r)$[21]:

S(q2)=πΔ2l2(1+q22l22)3/2,

where q$_{2}$ $=$ 2k$_{\rm F}\sin \theta/2$,k$_{\rm F}$ is the Fermi wavenumber,while $\vartriangle$ and $l$ are the average deviation and the correlation length of the high-$k$ dielectric/Ge interface,respectively. Thus,the scattering probability and relaxation time of the surface roughness scattering can be obtained through finding the scattering matrix element by substituting the Fourier transform of $H_{\rm SR}$ and Equation (14) into Equation (1). Further,according to the formula of $\mu _{\rm sr} =\frac{e \tau _{\rm sr} }{m^\ast }$,the mobility limited by surface roughness scattering can be described as:

1μsr=emdmE2effπ32π0(1cosθ)S(q2)dθ.

Assuming that an interface charge is located at $z=z_{0}$ along the high-$k$/Ge interface,the perturbation electrostatic potential caused by this charge can be obtained by solving Poisson' equation:

[ε(z)(r,z)]=(ρ0+ρind),

where $\rho_0$ and $\rho_{\rm ind}$ are the interface charges density and induced screening-charge density[20],respectively,and $\varepsilon (z)$ is the position-dependent permittivity overall. According to the results of Ando[20],the coulomb scattering matrix element can be expressed as:

Mcs(q3)=Niteε012(εox+εs)P0eq3z0q3+qs(Pav+δsP20),

δs=εsεoxεs+εox,

qs(q3)=e2md4πε0εs210f(b1xEf/kBT)1xdx,

P0=b3(b+q3)3,Pav=8b3+9b2q3+3bq238(b+q3)3,

b=[12e2md(Ndepl+1132Ns)/(ε0εs2)]1/3,

where $f$ is the Fermi Dirac distribution,$E_{\rm f}$ is the Fermi level,$b_1 =\frac{\hbar q^2}{8m_{\rm d} k_{\rm b} T}$,$q_{\rm s}$ is the wave-vector-dependent screening parameter,$b$ is a variational parameter,$N_{\rm it}$ is the areal density of the interface charges and q$_{3}$ $=k’- k is the change of wavenumber before and after scattering. Then,the scattering probability of the coulomb scattering can be written as:

Pcs(E)=1τ(E)=mdπ3π0|Mcs(q3)|2(1cosϕ)dϕ.

Thus,the averaged relaxation time over kinetic energy $E$ can be described as:

1τcs=E1Eτ(E)tialftialEdEE1f(E)dE,

where $E_{\rm 1}$ denotes the ground level of the first subband. Hence,the mobility limited by coulomb scattering can be calculated by $\mu _{\rm cs} =\frac{e\tau _{\rm cs} }{m^\ast }$.

Aside from the mechanisms mentioned above,the thickness of Ge film and the interface quality between the Ge film and the buried oxide layer in GeOI MOSFETs also have effects on the carrier mobility in the inversion channel. The smaller the thickness of Ge film ($T_{\rm GeOI})$ is,the more degraded the mobility is,due to the dominated scattering from the fixed charge at the Ge/buried oxide layer interface[17, 22] and from the quantum well produced by ultra-thin Ge film[23, 24]. Besides,the scattering potential for a hole in the i-th subband ($i$ $=$ 1,2,3,$\cdots$) produced by a variation of $T_{\rm GeOI}$ can be expressed as[25]:

VFLi(r)(dEidTGeOI)ΔFL(r),

where $E_{\rm i}$ is the eigenvalue of the subband and $\Delta{\rm FL}$(r) is the $T_{\rm GeOI}$ variation in the transport plane. Further,the scattering probability (reciprocal relaxation time) induced by the additional potential can be derived as:

PGeOI=1τGeOI=mdπ3(dEidTGeOI)2π0SFL(q4)ε2(q4)(1cosϕ)dϕ,

where ${\frac{{\rm d}E_{\rm i} }{{\rm d}T_{\rm GeOI} }}=-\frac{\pi ^2\hbar ^2i^2}{m^\ast T_{\rm GeOI}^3 }$,$S_{\rm FL}$(q$_{4})$ is the power spectrum density of the $T_{\rm GeOI}$ fluctuations[25],and $\varepsilon$(q$_{4})$ is the two-dimensional static dielectric function[26]. So,the mobility limited by the $T_{\rm GeOI}$ variation can be obtained by $\mu _{t_{\rm GeOI} } =\frac{e \tau_{\rm GeOI}}{m^\ast }$.

Obviously,the mobility is roughly proportional to $T^{6}_{\rm GeOI}$.

Based on Matthiessen's rule,the total effective mobility $\mu_{\rm eff}$ of holes in the inversion channel limited by all the above mechanisms can be calculated as: 1μeff=1μph+1μI+1μsr+1μcs+1μtGeOI.

In simulation,a part of the physical parameters of GeOI pMOSFETs,e.g. $T_{\rm GeOI}$ $=$ 53 nm,$T_{\rm oxb}$ $=$ 147 nm,CET $=$ 2.1 nm (capacitance equivalent thickness),$\varepsilon_{\rm ox}$ $=$ 10.2,$\varepsilon_{\rm oxb}$ $=$ 3.9,etc.,are the same as those in Reference [27],and the other parameters,e.g. $\eta$,$D_{\rm ac}$,$\rho$,$\varepsilon_{\rm s}$,etc.,are from References [11, 15, 28],or are determined by fitting with experimental results,e.g. $\Delta$,$l$,$N_{\rm it}$ ,etc.,as listed in Table1.

Table  1.  A part of the physical parameters used in simulation.
DownLoad: CSV  | Show Table

Figure3 shows a comparison between the simulated hole mobility and experimental data. For clearly analyzing the effects of the scattering mechanisms on hole mobility,the mobilities limited by different mechanisms are respectively plotted in Figure3,in which the hollow circles represent the mobility determined by the phonon and ionized impurity scattering,i.e.,bulk-lattice scattering mobility; the triangle symbol is the mobility limited by the coulomb scattering; the diamond symbol describes the mobility affected by the surface roughness scattering and the black solid line stands for the effective mobility calculated by Equation (26). As shown in Figure3,a good agreement of the simulated results with experimental data[27] is achieved. The slightly larger values than the experiment data under high fields originated from the fact that only a first-order approximation of the Taylor formula was employed when calculating the perturbation Hamiltonian in Equation (13). It can be observed from Figure3 that in the low-field regime,the coulomb scattering is the main limiting mechanism because as the electrical field increases in the low-field regime,the carrier density in the inversion channel is increased,which makes the coulomb screening parameter $q_{\rm s}$ [Equation (19)] and the variational parameter $b$ [Equation (21)] enhanced,increasing the carrier mobility; in the high-field regime,the surface roughness scattering becomes the dominant mechanism because a highly effective electric field would induce a large perturbation potential at the roughness surface,which produces a strong scattering on the transportation of holes in the inversion layer,thus leading to a reduction of the hole mobility. While the acoustic phonon scattering is dependent on temperature,the ionized impurity scattering is related to temperature and the doping concentration of the channel would mainly affect the peak value of the hole mobility,they are less sensitive to the effective electric field.

Figure  3.  Comparison between the simulated hole mobilities and the experimental data for GeOI pMOSFETs.

Normally,it is believed that the impurities in Ge are fully ionized at room temperature. So,the perturbation potential is increased as the doping concentration increases,which makes the ionized impurity scattering on carriers enhanced,thus degrading the mobility,as shown in Figure4. The hole mobility in the high-field regime tends to be consistent because the surface roughness is assumed to be the same,which is similar to that in Reference [29] (for Ge film thickness of 20-60 nm). However,the doping concentration of the channel should not be too low for suppressing the short channel effect[30]. In addition,it can be seen from Figure4 that the curves of mobility versus $E_{\rm eff}$ right shift as $N_{\rm d}$ increases,because a higher electric field is needed to realize the inversion of the channel as doping concentration increases.

Figure  4.  Hole mobility versus the effective electric field under different doping concentrations of the channel.

Figure5 depicts the change of the hole mobility with effective electric field for different $\Delta$ parameters. In the low-field regime,the change trend of hole mobility for different $\Delta $ parameters tends to be consistent since the coulomb scattering is the dominant mechanism,and nevertheless,the hole mobility is greatly degraded in the high-field regime as $\Delta $ increases since the surface roughness scattering plays a main role in this case,as mentioned above.

Figure  5.  Hole mobility versus the effective electric field for various surface roughness.

As compared with the $\Delta $ parameter,the correlation length ($l)$ has a smaller effect on the channel-hole mobility. However,for a given $E_{\rm eff}$ or $N_{\rm s}$,the power spectral density in Equation (13) is maximum when $l=\frac{1}{\sqrt 2 k_{\rm F} \sin \frac{\theta }{2}}$,and hence the surface roughness scattering is strongest. The above condition implies that when $N_{\rm s}$ $=$ 8 × 10$^{12}$ cm$^{-2}$,$l$ is $\sim $ 2 nm,comparable to the thermal DE Broglie wavelength ($k_{\rm th}^{-1}$ $\approx$ 2 nm)[31]. So,a smooth surface is very necessary to obtain a high mobility.

Figure6 is the hole mobility as a function of $E_{\rm eff}$ under different temperatures. Obviously,the hole mobility is decreased with the elevating temperature. This is because the lattice vibration is enhanced as temperature increases,which makes the phonon scattering increased. Under low temperatures (< 300 K),the ionized impurity concentration is increased with elevated temperature and accordingly,the ionized impurity scattering on channel carriers is gradually enhanced. Therefore,both the acoustic phonon scattering and the ionized impurity scattering become the dominant mechanisms at low temperatures. While temperature is above room temperature,all the impurities are fully ionized so that only acoustic phonon scattering is the main mechanism to limit the mobility,resulting in a weakened temperature dependence of the hole mobility,as shown in Figure6.

Figure  6.  Hole mobility versus the effective electric field under different temperatures.

The interface charges generate coulomb potential and hence give rise to coulomb scattering on hole carriers,leading to a lower mobility. As can be seen from Figure7,the higher the interface-charge areal density is,the lower the low-field hole mobility is,while the degradation of the high-field hole mobility gradually tends to be consistent because it is mainly determined by the surface roughness scattering,as mentioned above. In addition,the right shift of the mobility versus $E_{\rm eff}$ curves with the increase of the interface charges areal density is attributed to the increased threshold voltage of the device,which is obviously not beneficial to a reduction of power consumption. Therefore,a high quality high-$k$/Ge interface is highly desired to improve the carrier mobility in the inversion channel.

Figure  7.  Hole mobility versus the effective electric field under different interface charge areal densities.

Figure8 shows the $T_{\rm GeOI}$ dependence of the hole mobility in the inversion channel. When $T_{\rm GeOI}$ $>$ 10 nm,the mobility hardly changes with the thickness of the Ge film,and when $T_{\rm GeOI}$ < 10 nm,the mobility is obviously decreased as $T_{\rm GeOI}$ decreases and especially when $T_{\rm GeOI}$ < 5 nm,a serious degradation of the mobility is observed. This is because a very strong quantum well effect will appear in the case of $T_{\rm GeOI}$ < 10 nm especially $T_{\rm GeOI}$ < 5 nm,which will create a large additional potential[32] and a strong scattering on the channel carriers,resulting in an obvious reduction of the mobility in the low-field regime. In addition,this kind of scattering is inherently related to the size-induced quantization in the Ge film[25],which is different from the mechanism of the surface roughness scattering described in Section 2.3. Further,Figure9 illustrates a strong dependence between the mobility and $T_{\rm GeOI}$ under the weak fields or low inversion-charge densities. As can be seen,for $T_{\rm GeOI}$ < $\sim $ 5 nm,the hole mobility decreases with $T^{6}_{\rm GeOI}$,which is also explained in Reference [25]. On the contrary,a gradually weakened thickness dependence of the hole mobility can be found for $T_{\rm GeOI}$ $>$ $\sim $ 5 nm,e.g. $T_{\rm GeOI}$ $=$ 6.5,8,10 nm,etc. So,the thickness of Ge film is an important parameter in GeOI pMOSFETs.

Figure  8.  Hole mobility versus the effective electric field for different thicknesses of Ge film.
Figure  9.  Hole mobility versus thickness of Ge film for different inversion charge densities under the weak fields.

On the other hand,too thin Ge film would make the inversion channel closer to the buried oxide interface,which makes the channel carriers easily suffer from scattering of the fixed charge of the buried oxide layer,leading to a further reduction of the hole mobility,as calculated in Reference [22]. Therefore,in order to prevent the serious degradation of the hole mobility in the inversion layer,the thickness of the Ge film should not be too thin,for example,$T_{\rm GeOI}$ $=$ 10 nm.

Based on Fermi's Golden Rule,a physical model of the hole mobility for GeOI pMOSFETs has been established by comprehensively considering various kinds of scattering mechanisms. The validity of the model is confirmed by the relevant experimental data. Using the model,the physical mechanisms on the degradation of the mobility under different conditions are analyzed,and the simulation results show that (i) in the low-field regime,the hole mobility is determined by the coulomb scattering and the larger the interface-charge areal density is,the more serious the mobility degradation is; (ii) in the high-field regime,surface roughness scattering is the dominant mechanism on the degradation of the mobility and the smoother the surface is,the higher the mobility is; (iii) the acoustic phonon scattering becomes strong with elevated temperature,and at low temperatures,the ionized impurity scattering is also an important scattering mechanism besides the acoustic phonon scattering; (iv) a higher doping concentration of the channel could generate a more serious ionized impurity scattering,resulting in a lower hole mobility,however,to suppress the short channel effect,the doping concentration should not be too low; (v) in the case of $T_{\rm GeOI}$ < 10 nm,the scattering potential from the quantum well could induce a severe degradation of the hole mobility,and to maintain a high mobility,a $T_{\rm GeOI}$ of $\sim $10 nm is reasonable. In summary,a smooth surface,high quality high-$k$/Ge interface,reasonable doping concentration of the channel and thickness of Ge film are highly desired for enhancing the hole mobility of GeOI pMOSFETs.



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.  Comparison of watt-level output power CMOS PAs.

Figure 1.


.  Two types of power combining transformers. (a) PCT. (b) SCT.

Figure 2.


.  Layout of a PCT without power supply point.

Figure 3.


.  Layout of the improved PCT with power supply point.

Figure 4.


.  EM-simulated maximum available efficiency of the two PCTs.

Figure 5.


.  Layout of the proposed SCT.

Figure 6.


.  EM-simulated insertion loss of the SCT.

Figure 7.


.  Schematic diagram of the 2.4 GHz PA.

Figure 8.


.  Schematic diagram of the 1.95 GHz PA.

Figure 9.


.  Schematic of the 1.95 GHz power stage.

Figure 10.


.  Layout of the 2.4 GHz PAs. (a) PA1. (b) PA2.

Figure 11.


.  Bonding diagram of the 2.4 GHz PAs. (a) PA1. (b) PA2.

Figure 12.


.  Photograph of 2.4 GHz PAs test board. (a) PA1. (b) PA2.

Figure 13.


.  Measured $S$-parameters of the 2.4 GHz PAs.

Figure 14.


.  Measured power gain and PAE of the 2.4 GHz PAs.

Figure 15.


.  Measured intermodulation distortion in a two-tone test with 1 MHz tone spacing of the 2.4 GHz PA2.

Figure 16.


.  Layout of the designed 1.95 GHz PA.

Figure 17.


.  Maximum $S_{21}$ and the corresponding frequency versus gain control signal.

Figure 18.


.  Simulated $S_{11}$ and $S_{21}$ versus frequency.

Figure 19.


.  Simulated gains and PAEs in six power modes at 1.95 GHz.

Figure 20.


.  Simulated (a) ACPR and (b) AltCPR in six power modes at 1.95 GHz.

Figure 21.


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.   Summary of device sizes of the two 2.4 GHz PAs.

Table 1

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.   Summary of device sizes of the 1.95 GHz PA.

Table 2

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.   Performance comparison of watt-level 2.4 GHz linear CMOS Pas.

Table 3

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.   Performance comparison of linear CMOS Pas.

Table 4

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    Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. Journal of Semiconductors, 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002
    Z X Ren, K F Zhang, L Q Liu, C Li, X F Chen, D S Liu, Z L Liu, X C Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. J. Semicond., 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002.
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    Received: 03 March 2015 Revised: Online: Published: 01 September 2015

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      Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. Journal of Semiconductors, 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002 ****Z X Ren, K F Zhang, L Q Liu, C Li, X F Chen, D S Liu, Z L Liu, X C Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. J. Semicond., 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002.
      Citation:
      Zhixiong Ren, Kefeng Zhang, Lanqi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. Journal of Semiconductors, 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002 ****
      Z X Ren, K F Zhang, L Q Liu, C Li, X F Chen, D S Liu, Z L Liu, X C Zou. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS[J]. J. Semicond., 2015, 36(9): 095002. doi: 10.1088/1674-4926/36/9/095002.

      On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

      DOI: 10.1088/1674-4926/36/9/095002
      Funds:

      Project supported by the National Natural Science Foundation of China (No. 61076030).

      • Received Date: 2015-03-03
      • Accepted Date: 2015-04-15
      • Published Date: 2015-01-25

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