LETTERS
Zhang Feng, Feng Wei, Cui Hao, Yang Yi, Huang Lingyi and Hu Weiwu
Abstract: This paper describes the design of a low voltage differential signal (LVDS) transmitter and receiver with high speed and low power for CPU,LCD,FPGA,and other fast links.In the proposed transmitter,a stable reference and a common mode feedback circuit are integrated into the LVDS drivers,which enable the transmitter to tolerate variations of process,temperature,and supply voltage.The proposed receiver implements a rail-to-rail amplifier architecture that allows a 1.6Gb/s transmission.The transmitter and receiver are implemented in HJ TC 3.3V,0.18μm CMOS technology.The experimental results demonstrate that the transmitter and receiver reach 1.6Gb/s.The transmitter and receiver pad cells exhibit a power consumption of 35 and 6mW,respectively.
Key words: LVDS, rail to rail, low power
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Received: 18 August 2015 Revised: 29 December 2007 Online: Published: 01 May 2008
| Citation: |
Zhang Feng, Feng Wei, Cui Hao, Yang Yi, Huang Lingyi, Hu Weiwu. A 0.18μm Transmitter and Receiver with High Speed and Low Power[J]. Journal of Semiconductors, 2008, 29(5): 836-840.
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Zhang F, Feng W, Cui H, Yang Y, Huang L Y, Hu W W. A 0.18μm Transmitter and Receiver with High Speed and Low Power[J]. J. Semicond., 2008, 29(5): 836.
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