| Citation: |
Yu Yang, Zhao Qian, Shao Zhibiao. A Low Power SRAM/SOI Memory Cell Design[J]. Journal of Semiconductors, 2006, 27(2): 318-322.
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Yu Y, Zhao Q, Shao Z B. A Low Power SRAM/SOI Memory Cell Design[J]. Chin. J. Semicond., 2006, 27(2): 318.
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A Low Power SRAM/SOI Memory Cell Design
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Abstract
A modified four transistor (4T) self-body-bias structured SRAM/SOI memory cell is proposed.The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p+ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM.Furthermore,this structure can operate safely with a 0.5V supply voltage,which may be prevalent in the near future.Finally,compared to conventional 6T CMOS SRAM,this structure’s transient responses are normal and its power dissipation is 10 times smaller.-
Keywords:
- SRAM/SOI,
- memory cell,
- self body bias,
- low power
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References
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Proportional views
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