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J. Semicond. > 2019, Volume 40 > Issue 12 > 122901

ARTICLES 

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

C. Usha and P. Vimala

+ Author Affiliations

 Corresponding author: C. Usha, usha.chintu.dec14@gmail.com

DOI: 10.1088/1674-4926/40/12/122901

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Abstract: This paper presents a compact two-dimensional analytical device model of surface potential, in addition to electric field of triple-material double-gate (TMDG) tunnel FET. The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source. The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage, lateral and vertical electric field. Because the TMDG TFET has a simple compact structure, the surface potential is computationally efficient and, therefore, may be utilized to analyze and characterize the gate-controlled devices. Furthermore, using Kane's model, the current across the drain can be modeled. The graph results achieved from this device model are close to the data collected from the technology computer aided design (TCAD) simulation.

Key words: triple-material double-gate TFETsurface potentiallateral and vertical electric fielddrain currentTCAD simulation

Over the past few decades, the performance of metal–oxide–semiconductor field-effect transistors (MOSFETs) has greatly improved thanks to their incessant and aggressive scaling. CMOS transistors scaling exhibits several short channel effects (SCEs). The short channel effects in MOSFETs are drain induced barrier lowering (DIBL), high leakage currents during OFF-state, high subthreshold slope (SS) and others. These effects lead to greater static power consumption and evil switching characteristics. Hence, substitute, innovative devices are introduced, among which tunneling field-effect transistor (TFET) is a promising candidate[14]. TFET operates based on BTBT process where electrons tunnel from valance band states to the conduction band state of the channel. Therefore, carriers with high energy are filtered out through the semiconductor bandgap, so its subthreshold slope TFET is < 60 mV/decade, though semiconductor bandgap carriers with higher energy levels are filtered out[5]. The output characteristic of TFET shows a delayed saturation. Therefore, TFETs should be designed carefully. The utility of TFET device is severely limited by the strong drain induced barrier lowering (DIBL)[6].

Numerous analytical models are carried out in the literature[715]. Many one-dimensional analytical models assume a constant electric field over the source channel junction to derive the current[710]. Many two-dimensional analytical models are based on TFET to calculate the tunneling generation rate using a two-dimensional Poisson’s equation, while the tunneling current has been computed by using surface potential equations[1113]. A number of analytical models were proposed for SMGTFET[719]. Many TFET with DM gates have been proposed, in which the OFF-state current is reduced due to minimum surface potential and adverse lateral electric field across the channel[2028]. A TFET with triple material was proposed in which TFET will tunnel carriers from source side to drain side in two directions due to shift of the tunneling junction. Analytical modeling of TMGTFET is very complex to analyze[26]. However, precise analytical models for TMGTFET are required. Thus, the main objective of this paper is to develop an analytical model for TMDGTFET by using a parabolic approximation approach. Using two-dimensional Poisson’s equations, we model surface potential, lateral and vertical electric field and drain current in simpler equations. The analytical model developed in this paper is useful for prognostic compact modeling of TMDGTFET, which includes analysis of the device physics. Section 2 explains the device parameters and structure, with three metal work function. The two-dimensional analytical model for TMDGTFET is derived using a two-dimensional Poisson’s equation for the various parameters in Section 3. Meanwhile, Section 4 includes the result and discussion with simulation graphs. Finally, the model is concluded in Section 5.

The schematic of a triple-material double-gate tunneling FET shown in Fig. 1, where M1, M2 and M3 are three different metals having different work function: Cobalt(ϕm1 = 5 eV), Iron(ϕm2 = 4.7 eV) and Chromium(ϕm3 = 4.5 eV) in the channel region. Both the back and front gates consists of three metals, with each channel length having L1, L2 and L3. The drain is n-type doped, the source is p-type doped, and the channel section is lightly doped with n-type. The effect of oxide charges is neglected because the channel is uniformly doped. tsi and tox are the thickness of channel and the oxide.

Figure  1.  (Color online) Schematic diagram of triple metal double-gate TFET (n-type).

The OFF-state current is quite low due to reduced work function ϕm and on source side there is no band overlap. The probability of tunneling of carriers on the source side increases because the band overlap increases as the tunneling width decreases. Hence, electrons tunnel from valence band to the conduction band of source in the intrinsic body and they then drift to drain by a process of drift diffusion. If there is an increase in ϕm, then the band diagram in ON-state does not change.

The potential distribution in the oxide region of the gate is distinguished by using a two-dimensional Poisson’s equation:

2ϕ(x,y)x2+2ϕ(x,y)y2=0.

(1)

The parabolic approximation approach is employed to resolve the two-dimensional Poisson’s equation for TMDG TFET. The parabolic method is used to calculate the potential distribution over the two-dimensional space (along device depth and device length) and an equation for the potential is given as follows

ϕ(x,y)=C0(x)+C1(x)y+C2(x)y2.

(2)

C0(x), C1(x) and C2(x) are arbitrary constants, each constant is functions of x. Since the gate consists of three materials, the potential under each material M1, M2 and M3 are given in Eqs. (3)–(5), respectively

ϕ1(x,y)=C10(x)+C11(x)y+C12(x)y2,0xL1,

(3)

ϕ2(x,y)=C20(x)+C21(x)y+C22(x)y2,L1xL1+L2,

(4)

ϕ3(x,y)=C30(x)+C31(x)y+C32(x)y2,L1+L2xL1+L2+L3.

(5)

The boundary conditions required for the solution of Poisson’s equation are as follows.

dϕ1(x,y)dx=εoxεsiϕs1(x)ψg1tox,undermaterialM1aty=0,

(6)

dϕ2(x,y)dx=εoxεsiϕs2(x)ψg2tox,undermaterialM2aty=0,

(7)

dϕ3(x,y)dx=εoxεsiϕs3(x)ψg3tox,undematerialM3aty=0.

(8)

dϕ1(x,y)dx=εoxεsiψg1ϕs1(x)tox,undermaterialM1aty=tsi,

(9)

dϕ2(x,y)dx=εoxεsiψg2ϕs2(x)tox,undermaterialM2aty=tsi,

(10)

dϕ3(x,y)dx=εoxεsiψg3ϕs3(x)tox,undermaterialM3aty=tsi.

(11)

By applying the above boundary condition from Eq. (6) to Eq. (11) we obtain

C10=ϕs1(x),

(12)

C11=εoxεsi[ϕsiψg1tox],

(13)

C12=1tsiεoxεsi[ϕsiψg1tox],

(14)

C20=ϕs2(x),

(15)

C21=εoxεsi[ϕsiψg2tox],

(16)

C22=1tsiεoxεsi[ϕsiψg2tox],

(17)

C30=ϕs3(x),

(18)

C31=εoxεsi[ϕsiψg3tox],

(19)

C32=1tsiεoxεsi[ϕsiψg3tox].

(20)

ϕs1(0,0)=Vbi,

(21)

ϕs1(L1,0)=ϕs2(L1,0),

(22)

ϕs1x=ϕs2x,whenx=L1,

(23)

ϕs2(L1+L2,0)=ϕs3(L1+L2,0),

(24)

ϕs2x=ϕs3x,whenx=L1+L2,

(25)

ϕs3(L1+L2+L3,0)=Vbi+VDS.

(26)

By applying these boundary conditions, the calculated surface potential ϕs1(x), ϕs2(x) and ϕs3(x) is given in Eqs. (21)–(26)

ϕs1(x)=Aeλx+Beλx+ψg1,0xL1,

(27)

ϕs2(x)=Ceλ(xL1)+Deλ(xL1)+ψg2,L1xL1+L2,

(28)

ϕs3(x)=Eeλ(xL1L2)+Feλ(xL1L2)+ψg3,L1+L2xL1+L2+L3,

(29)

where

λ=2εoxεsitoxtsi

ψg1=Vgsϕm1+χ+Eg/2

ψg2=Vgsϕm2+χ+Eg/2

ψg3=Vgsϕm3+χ+Eg/2

Eg is the energy bandgap, Vgs is the gate voltage, q is elementary charge, VDS is the drain to source voltage, Vbi is the built in potential, εsi and εox is the relative permittivity of silicon and silicon dioxide, L is channel length, χ is electron affinity and ϕm is work function of metal. Solving the Eqs. (27)–(29) we obtain A, B, C, D, E and F.

A=(Vbiψg1)eλ(L1+L2+L3)(Vbi+VDSψg3)+(ψg1ψg2)coshλ(L2+L3)+(ψg2ψg3)coshλL3eλ(L1+L2+L3)eλ(L1+L2+L3)

(30)

B=(Vbi+VDSψg3)(Vbiψg1)eλ(L1+L2+L3)(ψg1ψg2)coshλ(L2+L3)(ψg2ψg3)coshλL3eλ(L1+L2+L3)eλ(L1+L2+L3)

(31)

C=AeλL1+ψg1ψg22,

(32)

D=BeλL1+ψg1ψg22,

(33)

E=CeλL21+ψg2ψg32,

(34)

F=DeλL2+ψg2ψg32,

(35)

The lateral electric field Ex and vertical electric field Ey are found by deriving potential with respect to x and y, respectively. The lateral electric field is given in Eqs. (36)–(38) as

E1x(x)=dϕs1(x)dx=Aλeλx+Bλeλx,0xL1

(36)

E2x(x)=dϕs2(x)dx=Cλeλ(xL1)+Dλeλ(xL1),L1xL1+L2,

(37)

E3x(x)=dϕs3(x)dx=Eλeλ(xL1L2)+Fλeλ(xL1L2),L1+L2xL1+L2+L3.

(38)

The vertical electric field is given in Eqs. (39)–(41) as

E1y(x)=dϕ1(x,y)dy=C11(x)2yC12,0xL1,

(39)

E2y(x)=dϕ2(x,y)dy=C21(x)2yC22,L1xL1+L2,

(40)

E3y(x)=dϕ3(x,y)dy=C31(x)2yC32,L1+L2xL1+L2+L3.

(41)

The current in TMDG TFET depends on the BTBT of electrons from source valance band to conduction band of channel region, which is given as

IDS=qGdxdy,

(42)

where generation rate (G) can be calculated using Kane’s model which is given as

G(E)=A1ED1exp(B1E),

(43)

where A1 = 4 × 1014 cm–1/2V–5/2s–1 and B1 = 1.9 × 107 V/cm are the Kane’s parameters, E the magnitude of the electric field which is defined as

E=Ex+Ey.

Our proposed models are verified using two-dimensional numerical simulation. Fig. 1 gives a cross-sectional view of the proposed model TM-DG TFET, in which both front and back gates are composed of three materials with three various work functions. Fig. 2 provides the plot of surface potential versus position along the channel, for TM-DG TFET with different combinations channel length ratios, such as 1 : 1 : 1, 3 : 2 : 1 and 1 : 2 : 3 for a total channel length; i.e., L = 120 nm, VGS = 0.25, VDS = 0.5 and tox = 2 nm, respectively. The TM-DG TFET potential graph provides enhanced screening of channel space with respect to the first metal to be depleted from potential variation. The 3 : 2 : 1 device model needs high vitality to provide higher potential boundary as compared with other structures, with an increase in power supply to a substantial threshold voltage. In addition, the movement of carriers is decreased due to substantial potential barrier at the source side. The 1 : 2 : 3 device model outshines because of its enhanced carrier transport effectiveness.

Figure  2.  (Color online) Surface potential variation along the position of channel from the p-type doped source to n-type doped drain with different L1 : L2 : L3 ratio for VGS = 0.25 V, VDS = 0.5 V, and tox = 2 nm.

Fig. 3 demonstrates the correlations of lateral electric field across the channel for TM-DG TFET structures for Vgs = 0.25, Vds = 0.5 and tox = 2 nm. The two peaks obtained in the electric field profile of TMDG structure indicate appropriate carrier transport efficiency and an appropriate average electric field along the channel. The extra peak in electric field increases the speed of the carriers in the channel, along these lines guaranteeing a vertical extent gate transport effectiveness to provide more quantities of carriers to drain. In addition, at the drain side a reduced peak of electric field appeared to offer an extra advantage of giving higher resistance to HCEs. Among the different TM-DG structures, TM-DG TFET (1 : 2 : 3) lateral electric field has a peak that is closest to the region of source, consequently guaranteeing a peak in its carrier’s speed closest to the source. This brings about the extreme refinement in the carrier transport effectiveness, influential transconductance, and higher drain current.

Figure  3.  (Color online) Lateral electric field along the position of channel from the p- type doped source to the n- type doped drain with different L1 : L2 : L3 ratio for VGS = 0.25 V, VDS = 0.5 V, and tox = 2 nm.

Fig. 4 shows surface potential variation versus position across the channel with Vgs constant, for different drain to source voltages (Vds). The potential increases only under third metal (M3) and no change under metal M1 and M2, as Vds increases. The lateral electric field variation for different Vds with constant Vgs shows a change in the drain side, which is shown in Fig.5. Fig. 6 shows the surface potential variation for different gate to source voltages (Vgs), while the Vds constant changes the surface potential throughout the channel. A variation of the lateral electric field along the channel length for different gate to source (Vgs) with constant Vds shows that there is a change in both source and drain side, as displayed in Fig. 7. The region under Metal 1 is reduced because the electric field is high at the source channel junction, which reduces the tunneling path. Fig. 8 shows the vertical electric field along the channel with VGS = 0.25 V, VDS= 0.5 V, and tox = 2 nm. The vertical electric field has ae peak when the work function of the metal varies. The first peak is obtained when carriers transfer from M1 to M2 and second peak is obtained from M2 to M3.

Figure  4.  (Color online) Surface potential across channel length L = 120 nm and VGS = 0.25 V with different VDS = 0.25, 0.5, and 1 V.
Figure  5.  (Color online) Lateral electric field across the channel length L = 120 nm, VGS = 0.25 V for different VDS = 0.25, 0.5 and 1 V.
Figure  6.  (Color online) Surface potential along the channel with length L = 120 nm and VDS = 0.5 V for different VGS = 0.2, 0.4, and 0.6 V.
Figure  7.  (Color online) Lateral electric field profile for channel length L = 120 nm and VDS = 0.5 V for different gate voltages.
Figure  8.  (Color online) Vertical electric field along the channel for VGS = 0.25 V, VDS = 0.5 V, and tox = 2 nm.

The IdVGS characteristic for different oxide thickness is shown in Fig. 9. To obtain a high ON–OFF current ratio, Fig. 10 shows variation of IdVGS characteristic for different body thicknesses. A reduction in the body thickness helps to increase the current of the TFET, due to which the tunneling path is reduced with an exponential increase in tunneling probability. The IdVGS characteristics for different work function combination are shown in Fig. 11. The tunneling current increases when the work function of M1 increases.

Figure  9.  (Color online) IdVGS characteristics on a linear scale for VDS = 0.5 V and tsi = 5 nm for different oxide thickness.
Figure  10.  (Color online) IdVGS characteristics on a linear scale for VDS = 0.5 V and tox = 2 nm for different channel thickness.
Figure  11.  (Color online) IdVGS characteristics on a linear scale for VDS = 0.5 V and for a three different metal work function.

This paper proposes analytical modeling of a triple-material double-gate TFET. The tunneling path is modulated by the carriers over the channel due to the different work functions of the metals. The TM-DG TFET provides the better carrier transport efficiency, has higher resistance to HCEs, and obtains a high ON-OFF current ratio. Hence, TFET is strong promising behavior device that can be used in low-power applications.

This work was supported by Women Scientist Scheme-A, Department of Science and Technology, New Delhi, Government of India, under the Grant SR/WOS-A/ET-5/2017.



[1]
Toh E H, Wang G H, Samudra G, et al. Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J Appl Phys, 2008, 103, 104504 doi: 10.1063/1.2924413
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Seabaugh A C, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE, 2010, 98, 2095 doi: 10.1109/JPROC.2010.2070470
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Boucart K, Ionescu A M. A new definition of threshold voltage in tunnel FETs. Solid State Electron, 2008, 52, 1318 doi: 10.1016/j.sse.2008.04.003
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Vandenberghe W, Verhulst A, Greseneken G, et al. Analytical model for tunnel field- effect transistor. Proc MELECON, 2008, 923
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Fig. 1.  (Color online) Schematic diagram of triple metal double-gate TFET (n-type).

Fig. 2.  (Color online) Surface potential variation along the position of channel from the p-type doped source to n-type doped drain with different L1 : L2 : L3 ratio for VGS = 0.25 V, VDS = 0.5 V, and tox = 2 nm.

Fig. 3.  (Color online) Lateral electric field along the position of channel from the p- type doped source to the n- type doped drain with different L1 : L2 : L3 ratio for VGS = 0.25 V, VDS = 0.5 V, and tox = 2 nm.

Fig. 4.  (Color online) Surface potential across channel length L = 120 nm and VGS = 0.25 V with different VDS = 0.25, 0.5, and 1 V.

Fig. 5.  (Color online) Lateral electric field across the channel length L = 120 nm, VGS = 0.25 V for different VDS = 0.25, 0.5 and 1 V.

Fig. 6.  (Color online) Surface potential along the channel with length L = 120 nm and VDS = 0.5 V for different VGS = 0.2, 0.4, and 0.6 V.

Fig. 7.  (Color online) Lateral electric field profile for channel length L = 120 nm and VDS = 0.5 V for different gate voltages.

Fig. 8.  (Color online) Vertical electric field along the channel for VGS = 0.25 V, VDS = 0.5 V, and tox = 2 nm.

Fig. 9.  (Color online) IdVGS characteristics on a linear scale for VDS = 0.5 V and tsi = 5 nm for different oxide thickness.

Fig. 10.  (Color online) IdVGS characteristics on a linear scale for VDS = 0.5 V and tox = 2 nm for different channel thickness.

Fig. 11.  (Color online) IdVGS characteristics on a linear scale for VDS = 0.5 V and for a three different metal work function.

[1]
Toh E H, Wang G H, Samudra G, et al. Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J Appl Phys, 2008, 103, 104504 doi: 10.1063/1.2924413
[2]
Koswatta S O, Lundstrom M S, Nikonov S E, et al. Performance comparison between p–i–n tunneling transistors and conventional MOSFETs. IEEE Trans Electron Devices, 2009, 56, 456 doi: 10.1109/TED.2008.2011934
[3]
Seabaugh A C, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE, 2010, 98, 2095 doi: 10.1109/JPROC.2010.2070470
[4]
Saurabh S, Kumar M J. Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices, 2011, 58, 404 doi: 10.1109/TED.2010.2093142
[5]
Gnani E, Gnudi A, Reggiani S, et al. Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model. Solid-State Electron, 2013, 84, 96 doi: 10.1016/j.sse.2013.02.012
[6]
Boucart K, Ionescu A M. A new definition of threshold voltage in tunnel FETs. Solid State Electron, 2008, 52, 1318 doi: 10.1016/j.sse.2008.04.003
[7]
Vandenberghe W, Verhulst A, Greseneken G, et al. Analytical model for tunnel field- effect transistor. Proc MELECON, 2008, 923
[8]
Mojunder N N, Roy K. Band-to-Band tunneling ballistic low-power digital circuits and memories. IEEE Trans Electron Devices, 2009, 56, 2193 doi: 10.1109/TED.2009.2028394
[9]
Vandenberghe W, Verhulst A, Greseneken G, et al. Analytical model for point and line tunneling in a tunnel field-effect transistor. Proc Int Conf SISPAD, 2008, 137
[10]
Bardon M G, Neves H P, Puerd R, et al. Pseudo-two dimensional model for double gate tunnel FETs considering the junctions depletion regions. IEEE Trans Electron Devices, 2010, 57, 827 doi: 10.1109/TED.2010.2040661
[11]
Liu L, Mohata D, Datta S. Scaling length theory of double-gate interband tunnel field-effect transistors. IEEE Trans Electron Devices, 2012, 59, 902 doi: 10.1109/TED.2012.2183875
[12]
Lee M J, Choi W Y. Analytical model of single-gate silicon on insulator tunneling field effect tansistors (TFETs). Solid State Electron, 2011, 63, 110 doi: 10.1016/j.sse.2011.05.008
[13]
Zhang L, Lin X, He J, et al. Analytical charge model for double gate tunnel FETs. IEEE Trans Electron Devices, 2012, 59, 3217 doi: 10.1109/TED.2012.2217145
[14]
Pan A, Chui C O. A quasi-analytical model for double-gate tunneling field effect transistors. IEEE Trans Electron Devices, 2012, 33, 1468 doi: 10.1109/LED.2012.2208933
[15]
Bhushan B, Nayak K, Rao V R. DC compact model for SOI tunnel field-effect tansistors. IEEE Trans Electron Devices, 2012, 59, 2635 doi: 10.1109/TED.2012.2209180
[16]
Verhulst A S, Leoneli D, Rooyackers R, et al. Drain voltage dependent analytical model of tunnel field-effect transistor. J Appl Phys, 2011, 110, 024510 doi: 10.1063/1.3609064
[17]
Dobrovolsky V, Sizov F. Analytical model of the thin-film silicon-on-insulator tunneling field effect transistor. J App Phys, 2011, 110, 114513 doi: 10.1063/1.3660795
[18]
Wan J, Royer C L, Zaslavsky A, et al. A tunneling field effect transistor model conbining interband tunneling with channel transport. J Appl Phys, 2011, 110, 104503 doi: 10.1063/1.3658871
[19]
Vishnoi R, Kumar M J. Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport. IEEE Trans Electron Devices, 2014, 61, 1936 doi: 10.1109/TED.2014.2315294
[20]
Samuel T S A, Balamurugan N B. An analytical modeling and simulation of dual material double gate tunnel field effect transistor for low power applications. J. Elect Eng Technol, 2014, 9, 247 doi: 10.5370/JEET.2014.9.1.247
[21]
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    C. Usha, P. Vimala. A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure[J]. Journal of Semiconductors, 2019, 40(12): 122901. doi: 10.1088/1674-4926/40/12/122901
    C Usha, P Vimala, A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure[J]. J. Semicond., 2019, 40(12): 122901. doi: 10.1088/1674-4926/40/12/122901.
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    Received: 07 February 2019 Revised: 15 May 2019 Online: Accepted Manuscript: 13 August 2019Uncorrected proof: 13 August 2019Published: 09 December 2019

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      C. Usha, P. Vimala. A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure[J]. Journal of Semiconductors, 2019, 40(12): 122901. doi: 10.1088/1674-4926/40/12/122901 ****C Usha, P Vimala, A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure[J]. J. Semicond., 2019, 40(12): 122901. doi: 10.1088/1674-4926/40/12/122901.
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      C. Usha, P. Vimala. A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure[J]. Journal of Semiconductors, 2019, 40(12): 122901. doi: 10.1088/1674-4926/40/12/122901 ****
      C Usha, P Vimala, A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure[J]. J. Semicond., 2019, 40(12): 122901. doi: 10.1088/1674-4926/40/12/122901.

      A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

      DOI: 10.1088/1674-4926/40/12/122901
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