Citation: |
Jongwoon Yoon, Kwangsoo Kim. A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. Journal of Semiconductors, 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803
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J Yoon, K Kim, A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance[J]. J. Semicond., 2021, 42(6): 062803. doi: 10.1088/1674-4926/42/6/062803.
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A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance
DOI: 10.1088/1674-4926/42/6/062803
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Abstract
A split gate MOSFET (SG-MOSFET) is widely known for reducing the reverse transfer capacitance (CRSS). In a 3.3 kV class, the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field. In addition to the poor static performance, the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering (DIBL) caused by the high gate oxide electric field. As such, a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region (SG-CIMOSFET) is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance. The SG-CIMOSFET has a significantly low on-resistance (RON) and maximum gate oxide field (EOX) due to the central implant region. A grounded central implant region significantly reduces the CRSS and gate drain charge (QGD) by partially screening the gate-to-drain capacitive coupling. Compared to a planar MOSFET, the SG MOSFET, central implant MOSFET (CIMOSFET), the SG-CIMOSFET improve the RON×QGD by 83.7%, 72.4% and 44.5%, respectively. The results show that the device features not only the smallest switching energy loss but also the fastest switching time. -
References
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